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cml microcircuits communication semiconductors cmx838 frs/pmr446/gmrs family radio processor ? 2003 cml microsystems plc d/838/8 september 2003 provisional issue features and applications ? advanced one-of-any ctcss subaudio 50 tone processor ? fast decode time ? irq on any / all valid tones ? fast scan, group calling, auto response tone select and tone cloning? support ? supply independent output level ? rf synthesizer ? frs, pmr446 and gmrs rf channels ? configurable charge pump ? audio call tone generator ? audio processing ? mic amplifier ? pre/de-emphasis ? limiter with supply independent output level ? post limiter filtering ? mic, rx, and tx digital gain controls ? single and dual tx outputs ? signal source and external function switches ? low power, 3v to 5v supply ? powersave and sleep modes ? serial control interface micin rxin rxout txmod1 xtal aux i/o c-bus -rf in +rf in ref in sv ss sv dd xtal xtal i set cp out rf synthesizer s txmod2 micout timing generation irq rply data cmd data serial clock cs programmable sub- audio processor modulation output select and level control audio processor bias v bias v ss v dd a general purpose timer and tone generator the highly integrated cmx838 family radio processor includes subaudio, audio, and synthesizer functions to serve as the core engine for low cost, high performance frs, pmr446, and gmrs radio designs. its flexibility supports both simple and advanced multi-channel radios without cost penalties. integrated tx voltage reference and baseband clock generation circuits eliminate the need for external components. the cmx838?s features directly supports advanced end product functions such as: group calling, scanning, automatic scanner response tone setup, and tone cloning?. by using the cmx838 one global radio design can support multiple standards and markets. controlled via a serial interface (c-bus) the family radio processor operates from a 3v to 5v supply and is available in 28-pin tssop (cmx838e1) and 28-pin soic (CMX838D1) packages.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 2 d/838/8 contents section page 1 block diagram................................................................................................................6 2 signal list.................................................................................................................... ...7 3 external components....................................................................................................9 4 general description.....................................................................................................10 4.1 audio .......................................................................................................................... ..... 10 4.1.1 digitally controlled amplifiers (dca).....................................................................................10 4.1.2 transmit input amplifier ....................................................................................................... .11 4.1.3 audio switched capacitor filters ..........................................................................................11 4.1.3.1 pre-emphasis/low-pass filter.........................................................................................12 4.1.3.2 high-pass filter ............................................................................................................... 13 4.1.3.3 deviation limiter low-pass filter ....................................................................................13 4.1.4 de-emphasis .................................................................................................................... .....14 4.1.5 transmit audio path ............................................................................................................ ..14 4.1.6 receive audio path ............................................................................................................. ..15 4.1.7 audio path without de-emphasis or pre-emphasis...............................................................15 4.1.8 deviation limiter.............................................................................................................. ......16 4.2 tone signaling processor................................................................................................ 17 4.2.1 tone encoding/decoding .......................................................................................................17 4.2.2 subaudio rx and tx filter characteristics...........................................................................18 4.2.3 ctcss subaudio decoder and encoder tone set ..............................................................20 4.2.4 tone signaling processor configuration task descriptions .................................................21 4.2.4.1 normal run mode (task 0).............................................................................................21 4.2.4.2 reserved for test (task 1-3) .........................................................................................21 4.2.4.3 rx configuration.............................................................................................................22 4.2.4.4 tx configuration .............................................................................................................23 4.2.4.5 initialize and configure....................................................................................................24 4.3 rf synthesizer ................................................................................................................ 2 6 4.3.1 operating range and specifications.....................................................................................26 4.3.2 main divider................................................................................................................... ........26 4.3.3 phase detector & charge pump ...........................................................................................26 4.3.4 lock detect output............................................................................................................. ...27 4.3.5 reference circuits ............................................................................................................. ....27 4.4 baseband timing generation .......................................................................................... 27 5 software programming ...............................................................................................28 5.1 c-bus serial interface .................................................................................................... 28 5.1.1 8-bit c-bus register map ....................................................................................................29 5.1.2 16-bit c-bus register map ..................................................................................................30 5.1.2.1 general reset ($01).................................................................................................30 5.1.2.2 setup register ($80) ....................................................................................................31 5.1.2.3 audio control register ($81) ..................................................................................32 5.1.2.4 rx audio level control register ($82) ................................................................33
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 3 d/838/8 5.1.2.5 audio power and bandwidth control register ($83) ....................................34 5.1.2.6 txmod 1 & 2 control register ($88) .......................................................................35 5.1.2.7 synthesizer baseband clk control register ($89)........................................37 5.1.2.8 synthesizer general control register ($8a)..................................................38 5.1.2.9 synthesizer channel select register ($8b) .....................................................39 5.1.2.10 synthesizer status register ($8c) .......................................................................39 5.1.2.11 synthesizer 1st if offset register ($8d) ...........................................................40 5.1.2.12 16 bit subaudio task data register ($8e) ............................................................40 5.1.2.13 16 bit subaudio test data register ($8f).............................................................40 5.1.2.14 synthesizer test register ($90) .............................................................................40 5.1.2.15 16 bit subaudio test read data register ($91) ..................................................41 5.1.2.16 tone signaling control register ($93) ...............................................................41 5.1.2.17 subaudio status register ($94) ..............................................................................42 5.1.2.18 8 bit subaudio task data register ($95)...............................................................42 5.1.2.19 subaudio analog control register ($97)...........................................................43 6 application notes ........................................................................................................45 6.1 overview ....................................................................................................................... .. 45 6.2 basic frs radio architecture ......................................................................................... 46 6.3 cmx838 architectural overview ...................................................................................... 47 6.4 detailed cmx838 architecture......................................................................................... 47 6.4.1 audio processing............................................................................................................... ....48 6.4.2 tone signaling processor .....................................................................................................50 6.4.3 level control .................................................................................................................. .......52 6.4.4 synthesizer and charge pump .............................................................................................54 6.4.5 clock generation............................................................................................................... ....54 6.4.6 powersave functions ............................................................................................................ 55 6.5 control registers illustrated............................................................................................. 55 6.6 application examples ...................................................................................................... 58 6.6.1 cmx838 initialization.......................................................................................................... ...58 6.6.1.1 register descriptions: .....................................................................................................58 6.6.2 tx, subaudio encoding, single point modulation...................................................................58 6.6.2.1 register descriptions: .....................................................................................................59 6.6.3 rx, subaudio decode ctcss tone or tones.........................................................................60 6.6.3.1 register descriptions: .....................................................................................................60 6.6.4 rx, multiple subaudio tone detect - tone cloning? ............................................................62 6.6.4.1 register descriptions: .....................................................................................................62 7 performance specification..........................................................................................64 7.1 electrical performance..................................................................................................... 64 7.1.1 absolute maximum ratings...................................................................................................64 7.1.2 operating limits ............................................................................................................... .....64 7.1.3 operating characteristics ...................................................................................................... 65 7.1.4 timing......................................................................................................................... ...........68 7.2 packaging...................................................................................................................... .. 70
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 4 d/838/8 figures figure page figure 1: block diagram....................................................................................................... ...............................6 figure 2: recommended external components..................................................................................... ............9 figure 3: audio processing block diagram ...................................................................................... ................10 figure 4: digitally controlled amplifiers and switch matrix for adjusting and switching transmit audio and subaudio signals. .............................................................................................................. .................11 figure 5: tx input amplifier .................................................................................................. ............................11 figure 6: magnitude response for input low-pass filter. ....................................................................... .............12 figure 7: magnitude response for pre-emphasis filter. ......................................................................... ............12 figure 8: magnitude response of high-pass filter.............................................................................. ................13 figure 9: magnitude response of post-deviation limiter low-pass filter. ....................................................... .....13 figure 10: magnitude response of de-emphasis filter........................................................................... ............14 figure 11: transmit audio path frequency response with pre-emphasis..........................................................1 4 figure 12: receive audio path frequency response with de-emphasis. ...........................................................1 5 figure 13: audio path frequency response without pre-emphasis or de-emphasis..........................................15 figure 14: deviation limiter block diagram.................................................................................... ....................16 figure 15: subaudio block diagram ............................................................................................. ....................17 figure 16: subaudio rx filter gain for normal ctcss operation. ................................................................ ....18 figure 17: subaudio rx filter delay for normal ctcss operation................................................................ ....18 figure 18: subaudio tx level for normal ctcss operation (magnitude scale with respect to 0dbv) .............19 figure 19: subaudio tx filter delay for normal ctcss operation. ............................................................... ....19 figure 20: rf synthesizer block diagram....................................................................................... ..................26 figure 21: block diagram of main programmable divider. ........................................................................ ........26 figure 22: c-bus transaction timing diagram. .................................................................................. ...............28 figure 23: basic frs radio tx architecture .................................................................................... ................46 figure 24: basic frs radio rx architecture.................................................................................... ................46 figure 25: cmx838 main function blocks........................................................................................ ................47 figure 26: cmx838 main sections ............................................................................................... ....................47 figure 27: audio processing ................................................................................................... ..........................48 figure 28: example audio rx path .............................................................................................. ....................49 figure 29: example audio tx voice path........................................................................................ .................49 figure 30: example audio tx internally generated tone with loudspeaker enabled path ............................49 figure 31: tone signaling processor........................................................................................... .....................50 figure 32: example ctcss tone decoder path .................................................................................... .........51 figure 33: example ctcss tone encoder path .................................................................................... .........51 figure 34: example internal audio tone encoder path ........................................................................... ........52 figure 35: level control...................................................................................................... ..............................52 figure 36: example single point modulation level path......................................................................... .........53 figure 37: example two-point modulation level paths ........................................................................... ........53 figure 38: example single point modulation with varied subaudio level paths.............................................53 figure 39: synthesizer and charge pump........................................................................................ ................54 figure 40: clock generation ................................................................................................... ..........................54 figure 41: powersave scope and related control registers ...................................................................... ....55 figure 42: synthesizer to baseband clock control, $89 ......................................................................... .........55
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 5 d/838/8 figure 43: setup, $80......................................................................................................... ...............................56 figure 44: audio ($81), rx audio level ($82) and subaudio analog ($97) control ........................................56 figure 45: audio power and bandwidth control, $83............................................................................. ..........57 figure 46: txmod1 & txmod2 control, $88....................................................................................... ...........57 figure 47: application example tx, subaudio encoding, single point modulation .........................................60 figure 48: c-bus timing ....................................................................................................... ...........................69 figure 49: 28-pin tssop (e1) mechanical outline: order as part no. cmx838e1 ........................................70 figure 50: 28-pin soic (d1) mechanical outline: order as part no. CMX838D1 ...........................................70
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 6 d/838/8 1 block diagram ctcss decoders + ctcss encode rxin bias aux i/o c-bus serial interface divide 32/33 programmable divider 12 bit pr ogrammable reference counter phase detect or charge pump lock detect +rf i n -rf i n ref i n sv ss sv dd v bias xtal xtal i set cp out v ss v dd s baseband timing genera tion serial clock cs lpf v bias v bias v bias audio tone encode 0/180 phase 0/180 phase cmd data rply data irq txmod1 txmod2 rx notone/ tx dura tion timer voltage ref bpf micin micout pre lpf hpf lpf lim b in a in a out b out v bias voltage ref deemp voltage ref 1 0 v bias rxout figure 1: block diagram
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 7 d/838/8 2 signal list package signal description pin no. e1/d1 name type 1 rxin input receive input for both audio and subaudio signals. 2 aux i/o input/output when configured as an input this pin can be used to route externally generated ringing or alert signals to the rx and tx audio paths. when configured as an output this pin allows for monitoring internally generated ringing or alert signals. see section 4.2.4.5.3 3 micout output microphone amplifier feedback output. 4 micin input microphone amplifier input. this is the inverting input to a high gain opamp, suitable for use with common microphones. 5 cp out output synthesizer charge pump output. apply to external loop filter that drives the control input of an external vco 6 i set input synthesizer charge pump current control. connect via external resistor to sv ss to set charge pump current. 7 sv dd power synthesizer positive supply. this signal must be decoupled to sv ss by a capacitor mounted close to the device pins. 8 -rf in input synthesizer rf negative input. connect this pin to sv ss (synthesizer common) when a non-differential input signal is applied to +rf in . 9 +rf in input synthesizer rf positive input. 10 sv ss power synthesizer negative supply. 11 ref in input synthesizer reference oscillator input. 12 xtal input the input to the on-chip oscillator, for external xtal circuit or clock. this input should be connected to v ss , circuit common, when the device is configured to generate the xtal clock internally from the ref in clock. 13 xtal output inverted output of the on-chip crystal oscillator. this pin should not be connected (left open) when the device is configured to generate the xtal clock internally from the ref in clock. 14 cs input c-bus select data loading control function input. this input controls c-bus transfer initiation, completion and cancellation. 15 irq output interrupt output, logic '0' active level. this is a 'wire- orable' output, enabling the connection of multiple peripherals to 1 interrupt port on an external controller. this pin has a low impedance pull-down to logic "0" when active and a high-impedance when inactive. an external pull-up resistor is required. interrupt outputs may be configured via mask bits via c-bus commands. 16 rply data output reply data output to c-bus serial control port. output reply data bytes are synchronized to the clk clock input under the control of the cs input. this 3-state output is held at high impedance when not driving output data. 17 cmd data input command data input to c-bus serial control port. data is loaded into this device in 8-bit bytes, msb (d7) first, and lsb (d0) last, synchronized to the clk clock input.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 8 d/838/8 package signal description 18 serial clock input serial clock input to c-bus serial control port. this clock input controls transfer timing of commands and data to and from the device. 19 v ss power negative supply (circuit common) 20 txmod2 output transmit output 2 internally switch selected to be at any of (1) v bias , (2) transmit subaudio or (3) transmit audio summed with subaudio. 21 txmod1 output transmit output 1 internally switch selected to be at any of (1) v bias , (2) transmit audio or (3) transmit audio summed with subaudio. 22 v dd power positive supply. levels and voltages are dependent upon this supply. this signal must be decoupled to v ss by a capacitor mounted close to the device pins. 23 rxout output processed receive audio output. 24 b in input external processing path b input. 25 a in input external processing path a input. 26 v bias bi-directional a bias line for the internal circuitry, driven to v dd /2 by a high impedance source. this signal must be decoupled by a capacitor mounted close to the device pins. 27 b out output external processing path b output. this provides internal switch controlled access to either rx or tx audio signals for external processing such as expanding and unscrambling. 28 a out output external processing path a output. this provides internal switch controlled access to either rx or tx audio signals for external processing such as compressing and scrambling. table 1: signal list
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 9 d/838/8 3 external components a out b out v bias a in b in rxout v dd txmod1 txmod2 rxin irq rply data cmd data serial clock v ss cmx838e1 aux i/o micout micin cp out i set sv dd ref in -rf in +rf in sv ss xtal xtal cs c-bus serial control interface c1 c2 c3 c4 c5 c6 c7 c8 c15 c14 c13 c12 c11 c10 c9 u2 rf section ref osc vco from rf receiver from tone generator microphone rf section r1 r2 r4 r3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 c16 optional external audio processing figure 2: recommended external components r1 note 1 470k ? 5% c9 0.1f 20% r2 note 1 10k ? 5% c10 0.1f 20% r3 note 2 100k ? 10% c11 0.1f 20% r4 note 3 10% c12 0.1f 20% c1 0.1f 20% c13 0.1f 20% c2 0.1f 20% c14 0.1f 20% c3 note 1 33pf 20% c15 0.1f 20% c4 note 1 0.1f 20% c16 47.0pf 20% c5 note 2 0.1f 20% c6 0.1f 20% c7 0.1f 20% u2 speaker driver e.g. lm386 c8 0.1f 20% external components notes: 1. r1, r2, c3 and c4 form the gain components for the tx input amplifier (microphone amplifier). r1 should be chosen as required by the signal level, using the following formula: gain = -r1/r2 c3 x r1 should be chosen so as not to compromise the high frequency performance and c4 x r2 should be chosen so as not to compromise the low frequency performance. minimum suggested resistor value for r1 and r2 is 10k ? . 2. r3 and c5 values are dependent on microphone specifications. 3. r4 sets charge pump source current. see section 4.3.3.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 10 d/838/8 4 general description 4.1 audio the audio signal processing is designed to meet or exceed the requirements for basic audio filtering, gain control and deviation limiting in a frs radio. figure 3 is a block diagram of the audio circuitry. rxin tx subaudio (from on-chip subaudio tone generator) rxout aux i/o micin micout v ref lp pre 1 1 1 de 1 txmod1 a out b out a in b in deemphasis network deviation limiter and post-limiter lpf preemphasis or 2 order lpf nd 6 order hpf th lpf bypass limiter bypass audio input 1 select audio out select pre lpf ctrl hpf bypass debp rx audio out level audio level v ref v bias tos vlh vll tos txmod2 tx/rx tone generator auxpupen audio input 2 select txmod switch matrix and phase control see figure 4 figure 3: audio processing block diagram 4.1.1 digitally controlled amplifiers (dca) there are five dcas on-chip. they are used to set signal levels for audio in/out, subaudio in/out, receive audio out (volume control), modulation out1, and modulation out2. the audio in/out dca is adjustable in 0.5db steps over a +7.5db to ?7.5db range, see section 5.1.2.3. the volume control level dca is adjustable in 1.5db steps over a +12db to ?33db range, see section 5.1.2.4. the subaudio signal level in/out dca is adjustable in 0.5db steps over a +7.5db to ?7.5db range, see section 5.1.2.19 the modulation level controls are composed of two dcas, and a switch matrix, see figure 4. each modulation level dca, modulation out1 and modulation out2, can be switched to select either the output of the audio processor, or the output of the tone generator, or the addition of the audio and tone. in addition, there is an internally generated dc volume (labeled ?tos? in figure 4), which can be sent to the mod1 and mod2 dca?s. this signal is not generally applicable to frs radios. however, in some cases it may be desirable for testing or signal generation. the modulation out1 dca is adjustable in 0.5db steps over a +7.5db to ?7.5db range and the modulation out2 dca is adjustable in 0.25db steps over a +3.75db to -3.75db range, see section 5.1.2.6. to obtain inverse signals of mod 1and mod 2, the msb from the first byte (bit 7) and the msb from second byte (bit 15) have to set to logic 1, see section 5.1.2.6.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 11 d/838/8 txmod1 txmod2 v bias v bias v bias v bias v bias v bias tos subaudio tone in low r low r low r low r low r low r low r low r sum gain/attenuation gain = +/-1 tx/rx v bias gain/attenuation gain = +/-1 audio in figure 4: digitally controlled amplifiers and switch matrix for adjusting and switching transmit audio and subaudio signals. 4.1.2 transmit input amplifier the transmit input amplifier is a high gain low-noise operational amplifier. figure 5 is a simplified schematic showing the external components required for typical application with an electret condenser microphone. the external component values should be selected such that the feedback resistor will be greater than 10k ? and the minimum gain should be greater than 6db. in some cases, it may be desirable to implement a pre-emphasis characteristic of appropriately configuring the external component values around the tx input amplifier. in this case, the internal pre-emphasis should be bypassed (via c-bus). figure 5: tx input amplifier 4.1.3 audio switched capacitor filters four standard (composed of biquadratic sections) switched capacitor filters are used in the audio section. a pre-emphasis filter (+6db per octave from 300 to 3000 hz intended for transmit only) is implemented using 2 nd order switched capacitor network, which can be configured (via c-bus) to be a 2 nd order low-pass. a 6 th order high-pass filter is used to remove subaudible tones and bandwidth limit the incoming receive or transmit audio signal prior to being input to the limiter. a 4 th order low-pass filter follows the deviation limiter. this filter smoothes the transients generated by the deviation limiter. finally, a de-emphasis filter (-6db per octave from 300 to 3000 hz intended for receive only) is implemented using a 2 nd order switched capacitor network. see section 5.1.2 for details on configuring audio filters.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 12 d/838/8 4.1.3.1 pre-emphasis/low-pass filter figure 6 shows magnitude response for the input pre-emphasis/low-pass filter when programmed for low- pass mode. this mode would typically be selected when processing rx audio. -35 -30 -25 -20 -15 -10 -5 0 5 1000 10000 magnitude (db) frequency (hz) figure 6: magnitude response for input low-pass filter. figure 7 shows magnitude response for the input pre-emphasis/low-pass filter when programmed for pre- emphasis mode. this mode would typically be selected when processing tx audio. -20 -15 -10 -5 0 5 10 15 100 1000 10000 magnitude (db) frequency (hz) figure 7: magnitude response for pre-emphasis filter.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 13 d/838/8 4.1.3.2 high-pass filter figure 8 shows the magnitude response for the audio high pass filter. this filter?s purpose is to suppress subaudio tones when processing both rx and tx audio. -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 magnitude (db) frequency (hz) figure 8: magnitude response of high-pass filter. 4.1.3.3 deviation limiter low-pass filter the magnitude response for narrowband and wideband modes is shown in figure 9. narrow-band mode is generally required for transmitting in systems having rf channel bw 12.5khz (e.g. frs). -40 -35 -30 -25 -20 -15 -10 -5 0 5 1000 10000 magnitude (db) frequency (hz) wide band narrow band figure 9: magnitude response of post-deviation limiter low-pass filter.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 14 d/838/8 4.1.4 de-emphasis figure 10 shows magnitude response for the de-emphasis filter. this filter precedes the rx audio level control and is generally required to process rx audio. -20 -15 -10 -5 0 5 10 15 100 1000 10000 magnitude (db) frequency (hz) figure 10: magnitude response of de-emphasis filter. 4.1.5 transmit audio path overall magnitude response for the transmit audio path for wideband and narrowband with pre-emphasis is shown in figure 11. -80 -60 -40 -20 0 20 100 1000 10000 magnitude (db) frequency (hz) narrow band wide band figure 11: transmit audio path frequency response with pre-emphasis.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 15 d/838/8 4.1.6 receive audio path overall magnitude response for the receive audio path for wideband and narrowband with de-emphasis is shown in figure 12. -60 -50 -40 -30 -20 -10 0 10 20 100 1000 10000 magnitude (db) frequency (hz) narrow band wide band figure 12: receive audio path frequency response with de-emphasis. 4.1.7 audio path without de-emphasis or pre-emphasis the magnitude response for the audio path (could apply to transmit or receive) without the pre-emphasis or de-emphasis is shown in figure 13. -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 magnitude (db) frequency (hz) narrow band wide band figure 13: audio path frequency response without pre-emphasis or de-emphasis.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 16 d/838/8 4.1.8 deviation limiter the purpose of the deviation limiter is to limit the signal level at baseband prior to reaching the rf modulator. this is necessary to avoid co-channel interference as well as conform to the spectral constraints stipulated by regulatory agencies (e.g. fcc). figure 14 is a block diagram of the limiter circuitry. applying a dc voltage between v dd and v dd /2 to the reference input sets the maximum peak-to-peak signal level. this reference is internally set so the maximum signal level is 2.196v p-p and is constant over supply voltage. -1 ref i n tx audio limited speech to post deviation limiter filter figure 14: deviation limiter block diagram.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 17 d/838/8 4.2 tone signaling processor 4.2.1 tone encoding/decoding the tone signaling processor includes ctcss encode and decode functions as well as an audio frequency ringing/alert tone generator. the signaling processor is comprised of a configurable analog filter controlled by the subaudio analog control register ($97) and a digital processor controlled by configuration tasks. all device configuration data is passed over the device?s c-bus serial interface. the configuration tasks to setup the digital processor are simply c-bus transaction sequences, which download task argument data followed by a task request command. in typical applications, once the tone signaling processor is initialized, its primary behavior (ctcss encode and decode) is steered by the rx tx/ bit of the setup register ($80). the subaudio filter is shared between transmit and receive. it is used to remove the speech signal from the receive subaudio signal, leaving only the subaudible squelch signal as input to the digital processor. this filter is also used to smooth the digitally generated subaudible signals in the transmit mode. following the filter is a gain trimmer stage that can adjust the signal level 7.5db in 0.5db steps into the decoding section or out to the modulation section. approximately 20db of gain is provided in the receive path and 20db of attenuation in the transmit path. lpf1 ctcss encode ctcss decoders band gap reference audio tone encode v bias 0 1 rxin to modulation control block aux aux output control task external dc restoration subaudio filter input select subaudio hpf/lpf select subaudio filter output enable subaudio lpf1 gain 2 or 22db hpf lpf2 subaudio rx and tx levels -7.5 to 7.5db external dc restoration control with initialization tasks subaudio lpf2 gain 0 or -18db figure 15: subaudio block diagram
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 18 d/838/8 4.2.2 subaudio rx and tx filter characteristics -60 -50 -40 -30 -20 -10 0 10 20 30 10 100 1000 10000 magnitude (db) frequency (hz) figure 16: subaudio rx filter gain for normal ctcss operation. 0 0.005 0.01 0.015 0.02 10 100 1000 10000 delay (sec) frequency (hz) figure 17: subaudio rx filter delay for normal ctcss operation.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 19 d/838/8 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 magnitude (db) frequency (hz) figure 18: subaudio tx level for normal ctcss operation (magnitude scale with respect to 0dbv) 0 0.005 0.01 0.015 0.02 10 100 1000 10000 delay (sec) frequency (hz) figure 19: subaudio tx filter delay for normal ctcss operation.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 20 d/838/8 4.2.3 ctcss subaudio decoder and encoder tone set the cmx838 supports all popular subaudio tones with a unique, full performance, 'one-of-any' rapid detect capability that adds support for end product group calling and tone cloning? features. the digital processor essentially contains 51 decoders to analyze the receive signal. each decoder can independently be enabled or disabled via configuration tasks. the result of the subaudio signal analysis is available in the subaudio status register ($94). both a decode status bit, and a decoder index number are reported in the status register. the decode status bit is a logic one when an enabled decoder senses that the input signal matches its center frequency ? the index number will be that of the matching decoder. if the input signal does not contain a subaudio signal that matches an enabled decoder?s center frequency then the status bit is a logic zero ? in this case the decoder index number is reported as: a. 62 if there is a significant subaudio frequency present. b. 63 if the no tone timer has expired indicating there is no significant subaudio frequency present now. c. 0 if no subaudio signal has been seen since the subaudio processor was enabled or most recently placed in rx mode. d. any enabled index, if the last frequency measurement indicates that enabled tone may be present but has not yet been fully qualified. in tx mode the subaudio status is normally 0 and becomes 127 to indicate that the tx timer timed out. no. frequency (hz) no. frequency (hz) 1. 67.0 27. 159.8* 2. 69.3 28. 162.2 3. 71.9 29. 165.5* 4. 74.4 30. 167.9 5. 77.0 31. 171.3* 6. 79.7 32. 173.8 7. 82.5 33. 177.3* 8. 85.4 34. 179.9 9. 88.5 35. 183.5* 10. 91.5 36. 186.2 11. 94.8 37. 189.9* 12. 97.4 38. 192.8 13. 100.0 39. 196.6* 14. 103.5 40. 199.5* 15. 107.2 41. 203.5 16. 110.9 42. 206.5* 17. 114.8 43. 210.7 18. 118.8 44. 218.1 19. 123.0 45. 225.7 20. 127.3 46. 229.1* 21. 131.8 47. 233.6 22. 136.5 48. 241.8 23. 141.3 49. 250.3 24. 146.2 50. 254.1* 25. 151.4 51. user programmable 26. 156.7 * subaudible tones not included in tia-603 standard table 2: ctcss subaudio tone frequencies with their corresponding index number
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 21 d/838/8 4.2.4 tone signaling processor configuration task descriptions task id task description argument data in normal run mode 0 normal operation n/a reserved for test 1, 2, 3 special test functions n/a 4 enable/disable tone detector $95 5 program user defined subaudio tone $8e 6 adjust detector band width $8e rx configure 7 adjust no tone timer duration $8e 8 select sub-audio tone from preprogrammed list $95 9 program user defined subaudio tone $8e 10 program audio frequency ringing tone $8e tx configure 11 program tx timer $8e 12 enter fast initialization mode n/a 13 quickly enable/disable multiple detectors $95 14 configure aux pin as output $95 initialize and configure 15 soft reset n/a table 3: tone signaling processor initialization and configuration tasks tone signaling configuration tasks initialize the tone signaling processor. while the processor is running, either generating or detecting tones (controlled by the rx tx / bit of register $80), configuration tasks can be issued at a rate up to one per 250 s. the required argument register(s) should not be modified for at least this time after issuing a task. before issuing tasks that require argument data, first load the argument data in the argument data register. then load the desired task in the task field of the sub-audio general control register. the power control (i.e. enabled) and irq control (set however you want) should be logically or?ed with the desired task field to define the data to load in register $93. all c-bus writes to the tone signaling control register ($93), that enable (or keep enabled) the tone signaling processor, constitute issuing a task. before tasks are issued, the base band clocks must be setup. 4.2.4.1 normal run mode (task 0) to place the device in normal run mode issue task 0. in this mode, the tone signaling processor will either encode or decode depending on the rx tx / bit of register ($80). 4.2.4.2 reserved for test (task 1-3) do not issue tasks 1, 2 or 3 as these are reserved for test.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 22 d/838/8 4.2.4.3 rx configuration the following four tasks are used to control the decode behavior. 4.2.4.3.1 enable or disable tone detector (task 4) this task can be used to enable or disable tone detectors 1 to 51. tone detectors 1 to 50 have preset detection center frequencies while tone detector 51 has a user programmable center frequency. this task may be issued multiple times to configure a tone watch list. it is recommended not to include non tia-603 tones with their adjacent tia tones in a watch list. load argument in register $95, then issue task 4. repeat as needed to configure tone watch list. the argument data has the following format in the 8 bit task data register ($95). bit 7 bit 6 bits 5-0 1=enable 0=disable don?t care tone detector index number (1-51) additionally using index 63 can enable or disable all detectors while issuing just one task. enabling index 62 enables detection of all tia-603 tones. there is no single command to disable just the tia-603 tone detectors ? instead use index 63 to disable all detectors. for example to enable the 67hz tone detector: $95 0x81 // data to enable tone index 1 (67hz) $93 0x64 // task command to actually enable tone detector (and irq?s) 4.2.4.3.2 program user defined rx sub-audio tone (task 5) this task is used to program the center frequency of user programmable detector 51. load the argument value in register $8e, then issue task 5. the argument can be calculated according to the following equations. r n argument f n int r f int n + ? = ? ? ? ? ? ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? = 64 96 100000 511 5 . 0 100000 511 96 the argument data for 65 hz would be 31*64+14 = 0x07ce the programmed center frequency can be back calculated by: ) 511 ( 96 100000 r n f ? ? = in the example above the actual center frequency would be 64.97 hz. a c-bus sequence to setup tone detector 51 for 65hz and enable just it would be: $8e 0x07ce // argument data for user defined 65hz rx tone. $93 0x45 // task 5 command (no irq?s enabled) wait 250 s $95 0x3f // task 4 argument data to disable all decoders $93 0x44 // task 4 command (no irq?s enabled) wait 250 s $95 0xb3 // task 4 argument data to enable decoder 51 (the user definable one) $93 0x64 // task 4 command (with irq?s enabled) wait 250 s $93 0x60 // task 0 command (to place device normal run mode with irq?s enabled) // last command is not required if the device was already in normal run mode
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 23 d/838/8 4.2.4.3.3 adjust detector band width (task 6) the default bandwidth can be increased or decreased in increments of approximately 0.2% by loading a small positive or negative (2?s complement) value in register $8e and then issuing task 6. for the standard tia tone set the default bw setting is recommended ? so there is no need to adjust it. by default, the detector has a small bw hysteresis to minimize chatter in marginal conditions. 4.2.4.3.4 adjust no tone timer duration (task 7) the default no tone timer duration can be increased or decreased in increments of 60 s by loading a positive or negative (2?s complement) value in register $8e and then issuing task 7. () timerdelta int argument ? + = 667 . 16 5 . 0 where timerdelta is the amount by which you want to increase or decrease the default no tone timer in milliseconds. for example, to increase the default no tone timer by 10ms, load 167 (0xa7) into register $8e before issuing task 7. $8e 0x00a7 $93 0x67 // task 7 command to adjust no tone timer with irq?s enabled 4.2.4.4 tx configuration 4.2.4.4.1 select sub-audio tone from preprogrammed list (task 8) to select a preprogrammed sub-audio tone, load the index argument (1 to 50) in register $95 then issue task 8. for example to set up tx tone to 114.8 hz, the required c-bus sequence would be $95 0x11 $93 0x48 4.2.4.4.2 program user defined tx sub-audio tone (task 9) to program a user defined sub-audio tone, load the argument in register $8e then issue task 9. where the argument is defined by, ? ? ? ? ? ? ? ? + = 100000 65536 36 5 . 0 f int argument for example to set up tx tone to 65 hz, the required c-bus sequence would be $8e 0x05fe $93 0x49 4.2.4.4.3 program audio frequency ringing tone (task 10) to program a user-defined audio ringing tone, load the argument in register $8e then issue task 10. where the argument is defined by, ? ? ? ? ? ? ? ? + = 100000 65536 6 5 . 0 f int argument for example to set up the ringing tone frequency to 620 hz, the required c-bus sequence would be $8e 0x0986 $93 0x4a 4.2.4.4.4 program tx timer (task 11) load the argument in register $8e, then issue task 11. where the argument is defined by, the number of 4ms time units, ? ? ? ? ? ? ? ? ? + = ? 3 10 4 5 . 0 t int argument for example, to set up a recurring 10s tx timer with irq enabled set the argument to 2500 = 0x09c4 (at each irq the sub-audio status in binary is x111 1111, tx timer status is cleared to zero after reading status register). $8e 0x09c4 $93 0x4b
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 24 d/838/8 wait 250 s $93 0x60 (enable interrupts) 4.2.4.5 initialize and configure 4.2.4.5.1 enter fast initialization mode (task 12) issuing task 12 takes the tone signaling processor out of normal running mode and dedicates the processor to handling initialization tasks to increase the maximum task rate. in this mode neither the tone encoders nor the decoders run. to return to normal running mode issue task 0. in this fast initialization mode tasks can be issued at a rate of one per 50 s. ensure that the required argument registers are not updated for at least this time after a task is issued. 4.2.4.5.2 quickly enable/disable multiple detectors (task 13) issuing task 13 places the tone signaling processor in a mode that allows multiple detectors to be to be quickly configured. like for task 12 neither the tone encoders nor the decoders run in this mode. the argument data is defined as for task 4. this mode reverts to fast initialization mode when any other task is issued. to return to normal running mode issue task 0. the following example shows how to enable only tone detectors 1, 7, 10, 12, 18, and 20. multiple calls to task 4 can accomplish this, but would require more c-bus transactions and waiting 250 s after each task 4 call, but could allow the tone decoders to continue to run. // to disable all tone detectors and enter mode to quickly enable multiple detectors $95 0x3f $93 0x4d // value = 0x40 | 0x0d wait 250 s // to ensure device runs task 13 $95 0x81 // to enable tone detector 1 (67.0 hz) value = 0x80 | 0x01 wait 50 s // to ensure task completes $95 0x87 // to enable tone detector 7 (82.5 hz) wait 50 s // to ensure task completes $95 0x8a // to enable tone detector 10 (91.5 hz) wait 50 s // to ensure task completes $95 0x8c // to enable tone detector 12 (97.4 hz) wait 50 s // to ensure task completes $95 0x92 // to enable tone detector 18 (118.8 hz) wait 50 s // to ensure task completes $95 0x94 // to enable tone detector 20 (127.3 hz) wait 50 s // to ensure task completes // to place device back in normal running mode $93 power control + irq control + task 0
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 25 d/838/8 4.2.4.5.3 configure aux pin as output (task 14) task 14 can be used to select and enable various digital outputs at the aux pin. load the argument data in register $95 then issue the task. the argument data has the following format in the 8 bit task data register ($95). bit 7 bit 6-3 bit 2-0 (these bits are don?t care if bit 7 is a logic 0) 1=enable aux pin as output 0=enable aux pin as input don?t care bit 2 bit 1 bit 0 aux output signal 1 0 0 rx decode status bit 1 0 1 audio frequency ringing tone 1 1 0 output logic 0 1 1 1 output logic 1 for example to have the device produce a 620hz ringing tone frequency set up the ringing frequency with task 10 then enable the output with task 14. note that once the audio ringing generator is enabled the frequency can be changed by reissuing task 10. $8e 0x0986 // 620 hz $93 0x4a wait 250 s $95 0x85 $93 0x4e wait at least 250 s $8e 0x06c2 // 440 hz $93 0x4a 4.2.4.5.4 soft reset (task 15) the tone signaling processor must be fully initialized after the chip is powered up. after powering up, the first time the tone-signaling processor is enabled, it should be with the task field set to 15. this clears the configuration memory and reverts to fast initialization mode when any other task is issued. after all desired initialization is performed, return to normal running mode by issuing task 0. power up sequence //power up the device // issue general reset $01 // set up base band clocks before enabling the sub-audio processor $89 0xxx // specific setting depends on your system (see section 5.1.2.7) $8a 0xxx // specific setting depends on your system (see section 5.1.2.8) // issue sub-audio processor soft reset $93 0x4f // wait for soft reset to complete wait 250 s // set up tx sub-audio frequency $95 tx tone index $93 0x48 // set up one rx sub-audio frequency $95 (0x80 | rx tone index) $93 0x44 // setup normal run mode for sub-audio processor $93 (0x40 | irq control | task 0) // setup rx and tx sub-audio analog trimmers to 0db $97 0x1010 // setup other c-bus registers as needed (e.g. register $80 to select rx tx/ , $88 for tx mod 1 and mod 2 control, etc.)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 26 d/838/8 4.3 rf synthesizer this section describes the implemented core functions of an integer-n frequency synthesizer. this includes modules for the rf 32/33 prescaler, programmable divider, phase detector, lock indicator, reference counter and charge pump. the block diagram for the module is shown in figure 20. divide 32/33 programmable divider 12 bit programmable reference counter phase detector charge pump lock detect -rf in +rf in ref in sv ss i set cp out s sv dd figure 20: rf synthesizer block diagram. 4.3.1 operating range and specifications the rf synthesizer is capable of supporting narrowband (6.25khz < channel bw <25khz) applications in the rf range from 100mhz to 500mhz. in other words, there are no blind channels over this range. 4.3.2 main divider an input buffer amplifies and limits the rf signal from the vco to a level that drives the dual modulus prescaler. the main rf divider is implemented using the dual-modulus 32/33 prescaler in conjunction with a programmable counter. this counter is realized using two programmable counters ( a & m counters). the m -counter uses a 12-bit programming word and the a-counter uses a 5-bit word, see figure 21. divide 32/33 rf in programmable 5 bit a-counter programmable 12 bit m-counter to phase detector data w o r d 512 17 reset modulus figure 21: block diagram of main programmable divider. the forward division ratio, n, can be expressed as: n = (32m + a) where a and m represent the programmed data words. 4.3.3 phase detector & charge pump a phase/frequency detector is implemented where steps have been taken to remove the dead-band normally associated with this type of detector and charge pump arrangement. an external resistor, r set , sets i chp , the nominal charge pump current. the current through this resistor is set by a 1.26v on-chip reference at the i set pin where, i set = 1.26 r set. the magnitude of the charge pump current is either 40*i set or 80*i set depending upon the state of the ihl bit programmed through the c-bus serial interface, see section 5.1.2.8 for programming details. ihl = 0, i chp = 40*i set ihl = 1, i chp = 80*i set the value of r set can vary between about 50k ? and 250k ? . this gives a charge pump current range of 0.2ma to 2.0ma.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 27 d/838/8 4.3.4 lock detect output the lock detect status is active high when the phase error corresponds to a time difference of less than about 20ns, 40ns, 60ns, or 80ns at the phase detector comparison inputs. the comparison period is chosen using the lock delay bits of the channel select register ($8b). the lock status is updated according to the lock detect mode chosen using the synthesizer general control register ($8a). lock detect data is collected once every period of the reference signal. 4.3.5 reference circuits the input from the external crystal oscillator is buffered and amplified to cmos levels. this reference signal is then divided in frequency by a 12-bit programmable counter. the reference divider is loaded from a rom that yields one of four possible reference frequencies: 6.25khz, 12.5khz, 20khz, and 25khz. frequency selection is dependent on the rf service bits of the synthesizer general control register ($8a) or two of the channel select bits when generic rf service is chosen ($8b). 4.4 baseband timing generation internal baseband timing is developed from a configurable choice of two sources: a crystal clock signal (xtal/clock) or an externally applied synthesizer reference clock signal (ref in ). an on-chip crystal oscillator amplifier is provided to form a crystal oscillator via the addition of an external crystal. several frequency options are supported for both crystal and synthesizer clock source options. configuration details are described in section 5.1.2.7.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 28 d/838/8 5 software programming 5.1 c-bus serial interface c-bus is the serial interface used by a c to transfer data, control, and status information, to and from the internal registers of the chip. every transaction consists of one address byte that may be followed by one or two bytes of data. data sent from the c to the chip on the cmd data line is clocked in on the rising edge of serial clock. rply data sent from the chip to the c is valid when serial clock is high. see figure 22. this serial interface is compatible with most common c serial interfaces such as sci, spi, and microwire. cs a) single byte from c serial clock cmd data address (01 hex = reset) = level not important note: the serial clock line may be high or low at the start and end of each transaction. hi-z rply data 7 6 5 4 3 2 1 0 7 6 5 4 3 21 0 c) one address byte from c and 2 reply bytes from the chip cs serial clock hi-z address data from chip data from chip cmd data rply data 7 6 5 4 3 2 1 0 7 6 5 4 3 21 0 b) one address and 2 data bytes from c cs serial clock cmd data address hi-z data to chip data to chip rply data 7 6 5 4 3 21 0 7 6 5 4 3 21 0 7 6 5 4 3 2 1 0 figure 22: c-bus transaction timing diagram.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 29 d/838/8 5.1.1 8-bit c-bus register map 8 bit register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general reset [write $01] n/a audio path control setup register [write $80] tx enable input 1 control input 2 control output control unused audio filter bypass control audio control [write $81] pre-emphasis low-pass bypass control high- pass bypass control audio level +/- 7.5db in 0.5db steps rx volume control [write $82] limiter & limiter filter & de-emphasis bypass control volume control +12 to ?33db in 1.5db steps audio power and bw control [write $83] power control for mod 1 & 2 and micamp power control for audio filters and limiter power control for volume control audio band- width sel unused synthesizer baseband clk control [write $89] synthesizer & baseband clock source select synthesizer reference input frequency select xtal/clock input frequency select charge pump current synthesizer general control [write $8a] enable, powersave, & test mode control lock detector control & irq mask high low polarity rf system frs, gmrs, pmr 446, or generic reserved set to "0" lock detect window 20 to 80ns channel selection indexed control of valid frs, gmrs & pmr446 rf channels synthesizer channel sel [write $8b] in generic rf system mode (set in [sgc]) synthesized frequency is set via these bits and bits in [sbcc] & [sifos] registers synthesizer status [read $8c] lock algorithm status lock status of most recent 7 phase comparisons test 0 [write $90] synthesizer test modes tone signaling control [write $93] power control for subaudio subaudio irq control subaudio task selection subaudio status [read $94] [sas] synthesizer irq flag decode decoded tone index 8 bit subaudio task data [write $95] subaudio task data byte 8 bit subaudio test data [write $96] subaudio test data byte table 4: 8 bit registers
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 30 d/838/8 5.1.2 16-bit c-bus register map 16 bit register name bit 15 / bit 7 bit 14 / bit 6 bit 13 / bit 5 bit 12 / bit 4 bit 11 / bit 3 bit 10 / bit 2 bit 9 / bit 1 bit 8 / bit 0 mod 2 switch bank control 0/180 phase select sub- audio enable audio enable mod 2 level +/- 3.75db in 0.25db steps mod 1 switch bank control tx mod 1&2 control [write $88] 0/180 phase select sub- audio enable audio enable mod 1 level +/- 7.5db in 0.5db steps synthesizer 1 st if offset [write $8d] [sifos] signed 16 bit number proportional to if offset, automatically applied when device is in rx mode [sr] & one of three specific rf system modes (frs, gmrs, pmr 446) is selected in [sgc] in generic rf system mode (selected in [sgc]), synthesized frequency is set directly via these 16 bits and bits in [sbcc] & [scs] registers 16 bit subaudio task data [write $8e] subaudio task data word 16 bit subaudio test data [write $8f] subaudio test data word 16 bit subaudio test read data [read $91] subaudio test read word subaudio filter path control tx level control +/-7.5db in 0.5db steps subaudio analog control [write $97] subaudio filter path control rx level control +/-7.5db in 0.5db steps table 5: 16 bit registers 5.1.2.1 general reset ($01) the reset command has no data attached to it. application of the general reset, sets all write only register bits to ?0?.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 31 d/838/8 5.1.2.2 setup register ($80) transmit/ receive ( r x tx/ ) bit 7 in the audio section, this bit controls a single pole single throw switch in the audio path between the deviation limiter/low-pass filter and the transmit modulation digitally controlled amplifiers. a logic ?1? allows audio to flow between these blocks. in the synthesizer section, this bit in conjunction with the synthesizer intermediate frequency offset register (sifos register) allows for autonomous switching between two synthesizer frequencies (for example where the required receive frequency equals the transmit center frequency offset high or low by the radios first intermediate frequency). a logic ?1? will enables synthesis of the transmit frequency, while a logic ?0? enables the offset frequency. in the subaudio section, this bit enables the subaudio encoder (logic ?1?) or decoder (logic ?0?). audio input 1 select bit 6 and bit 5 a 3-1 mux allows audio to be selected from the microphone amplifier output, the receive input, or the auxiliary input. reference figure 3. bit 6 bit 5 result 0 0 no inputs selected. 1 0 aux i/o 0 1 rxin 1 1 micout audio input 2 select bit 4 and bit 3 a 3-1 mux allows audio to be selected from a in (external input), b in (external input), or the internal high-pass filter output. the external inputs are available for external audio processing such as companding and voice scrambling. reference figure 3. bit 4 bit 3 result 0 0 no inputs selected. 1 0 a in 0 1 b in 1 1 hpf out audio output select bit 2 and bit 1 a 3-1 mux allows audio to be directed to a out (external output), b out (external output), or to the internal deviation limiter/low-pass filter. the external outputs are available for external audio processing such as companding and voice scrambling. reference figure 3 bit 2 bit 1 result 0 0 no outputs active, a out and b out are held at v dd /2 1 0 a out selected, b out held at v dd /2. 0 1 b out selected, a out held at v dd /2 1 1 lpf/lim input bit 0 unused, must be set to logic 0 table 6: setup register ($80)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 32 d/838/8 5.1.2.3 audio control register ($81) pre- emphasis/lpf control (pre lpf ctrl) bit 7 and bit 6 the first stage of filtering following input mux 1 can be configured as a 2nd order low- pass filter, as a pre-emphasis network or bypassed. reference figure 3. bit 7 bit 6 result 0 0 pre-emphasis 0 1 low-pass filter 1 0 mute, output is held to v dd /2 1 1 bypass highpass filter bypass bit 5 when this bit is a logic ?1? the high-pass audio filter is bypassed. reference figure 3. audio level bit 4,3,2,1,0 the five least significant bits in this register are used to set the gain/attenuation of the audio level control as shown in the table below. this digitally controlled amplifier is located in the audio path between the input low-pass filter/pre-emphasis network and the 6 th order high-pass filter. its primary purpose is to trim the nominal audio level such that the dynamic range is maximized. 4 3 2 1 0 audio gain 0 0 0 0 0 off 0 0 0 0 1 -7.5db 0 0 0 1 0 -7.0db 0 0 0 1 1 -6.5db 0 0 1 0 0 -6.0db 0 0 1 0 1 -5.5db 0 0 1 1 0 -5.0db 0 0 1 1 1 -4.5db 0 1 0 0 0 -4.0db 0 1 0 0 1 -3.5db 0 1 0 1 0 -3.0db 0 1 0 1 1 -2.5db 0 1 1 0 0 -2.0db 0 1 1 0 1 -1.5db 0 1 1 1 0 -1.0db 0 1 1 1 1 -0.5db 1 0 0 0 0 0.0db 1 0 0 0 1 0.5db 1 0 0 1 0 1.0db 1 0 0 1 1 1.5db 1 0 1 0 0 2.0db 1 0 1 0 1 2.5db 1 0 1 1 0 3.0db 1 0 1 1 1 3.5db 1 1 0 0 0 4.0db 1 1 0 0 1 4.5db 1 1 0 1 0 5.0db 1 1 0 1 1 5.5db 1 1 1 0 0 6.0db 1 1 1 0 1 6.5db 1 1 1 1 0 7.0db 1 1 1 1 1 7.5db table 7: audio control register ($81)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 33 d/838/8 5.1.2.4 rx audio level control register ($82) limiter bypass bit 7 when this bit is a logic ?1?, the deviation limiter is bypassed. lowpass filter bypass bit 6 when this bit is a logic ?1?, the post deviation limiter low-pass filter is bypassed. de-emphasis bypass bit 5 when this bit is a logic ?1?, the de-emphasis network is bypassed. rx audio level bit 4,3,2,1,0 the five least significant bits in this register are used to set the gain/attenuation of the volume control according to the table below: 4 3 2 1 0 increment per step = 1.5db steps 0 0 0 0 0 off 0 0 0 0 1 -33.0db 0 0 0 1 0 -31.5db 0 0 0 1 1 -30.0db 0 0 1 0 0 -28.5db 0 0 1 0 1 -27.0db 0 0 1 1 0 -25.5db 0 0 1 1 1 -24.0db 0 1 0 0 0 -22.5db 0 1 0 0 1 -21.0db 0 1 0 1 0 -19.5db 0 1 0 1 1 -18.0db 0 1 1 0 0 -16.5db 0 1 1 0 1 -15.0db 0 1 1 1 0 -13.5db 0 1 1 1 1 -12.0db 1 0 0 0 0 -10.5db 1 0 0 0 1 -9.0db 1 0 0 1 0 -7.5db 1 0 0 1 1 -6.0db 1 0 1 0 0 -4.5db 1 0 1 0 1 -3.0db 1 0 1 1 0 -1.5db 1 0 1 1 1 0.0db 1 1 0 0 0 1.5db 1 1 0 0 1 3.0db 1 1 0 1 0 4.5db 1 1 0 1 1 6.0db 1 1 1 0 0 7.5db 1 1 1 0 1 9.0db 1 1 1 1 0 10.5db 1 1 1 1 1 12.0db table 8: rx audio level control register ($82)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 34 d/838/8 5.1.2.5 audio power and bandwidth control register ($83) tx mod and mic amplifier power control bit 7 and bit 6 these bits are dedicated to power control for the modulation digitally controlled amplifiers and the microphone amplifier bit 7 bit 6 power level setting 0 0 power down (off) 0 1 normal operation audio filter power control bit 5 and bit 4 these bits are dedicated to power control for the audio filters, the deviation limiter, and the audio level digitally controlled amplifier bit 5 bit 4 power level setting 0 0 power down (off) 0 1 normal operation rx audio out power control bit 3 and bit 2 these bits are dedicated to power control for the de-emphasis network and the rx audio out digitally controlled amplifier. bit 3 bit 2 power level setting 0 0 power down (off) 0 1 normal operation audio bandwidth control bit 1 a logic ?1? on this bit reduces the ?3db bandwidth of the post deviation limiter low-pass filter from 3.5khz to 3.0khz. the narrow band setting is intended for radio systems with rf channel bandwidths 12.5khz. bit 0 unused, must be set to logic ?0? table 9: audio power and bandwidth control register ($83)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 35 d/838/8 5.1.2.6 txmod 1 & 2 control register ($88) txmod2 ? reference figure 3 phase control 0 = 0 1 = 180 bit 15 subaudio signal enable bit 14 audio signal enable bit 13 mod2 phase control (bit 15) 0 = 0 , 1 = 180 subaudio signal enable (bit 14) audio signal enable (bit 13) bias 0 0 0 audio 0 0 1 tone 0 1 0 audio + tone 0 1 1 inv (bias + offset) 1 0 0 inv (audio) 1 0 1 inv (tone) 1 1 0 inv (audio + tone) 1 1 1 mod2 gain bit 12, 11, 10, 9, 8 bit 12 bit 11 bit 10 bit 9 bit 8 mod. 2 gain 0 0 0 0 0 off 0 0 0 0 1 -3.75db 0 0 0 1 0 -3.50db 0 0 0 1 1 -3.25db 0 0 1 0 0 -3.00db 0 0 1 0 1 -2.75db 0 0 1 1 0 -2.50db 0 0 1 1 1 -2.25db 0 1 0 0 0 -2.00db 0 1 0 0 1 -1.75db 0 1 0 1 0 -1.50db 0 1 0 1 1 -1.25db 0 1 1 0 0 -1.00db 0 1 1 0 1 -0.75db 0 1 1 1 0 -0.50db 0 1 1 1 1 -0.25db 1 0 0 0 0 0.00db 1 0 0 0 1 0.25db 1 0 0 1 0 0.50db 1 0 0 1 1 0.75db 1 0 1 0 0 1.00db 1 0 1 0 1 1.25db 1 0 1 1 0 1.50db 1 0 1 1 1 1.75db 1 1 0 0 0 2.00db 1 1 0 0 1 2.25db 1 1 0 1 0 2.50db 1 1 0 1 1 2.75db 1 1 1 0 0 3.00db 1 1 1 0 1 3.25db 1 1 1 1 0 3.50db 1 1 1 1 1 3.75db table 10: txmod2 control register ($88)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 36 d/838/8 txmod1 - reference figure 3 phase control 0 = 0 1 = 180 bit 7 subaudio signal enable bit 6 audio signal enable bit 5 mod1 phase control (bit 7) 0 = 0 , 1 = 180 subaudio signal enable (bit 6) audio signal enable (bit 5) bias 0 0 0 audio 0 0 1 tone 0 1 0 audio + tone 0 1 1 inv (bias + offset) 1 0 0 inv (audio) 1 0 1 inv (tone) 1 1 0 inv (audio + tone) 1 1 1 mod1 gain bit 4-0 bit 4 bit 3 bit 2 bit 1 bit 0 mod. 1 gain 0 0 0 0 0 off 0 0 0 0 1 -7.5db 0 0 0 1 0 -7.0db 0 0 0 1 1 -6.5db 0 0 1 0 0 -6.0db 0 0 1 0 1 -5.5db 0 0 1 1 0 -5.0db 0 0 1 1 1 -4.5db 0 1 0 0 0 -4.0db 0 1 0 0 1 -3.5db 0 1 0 1 0 -3.0db 0 1 0 1 1 -2.5db 0 1 1 0 0 -2.0db 0 1 1 0 1 -1.5db 0 1 1 1 0 -1.0db 0 1 1 1 1 -0.5db 1 0 0 0 0 0.0db 1 0 0 0 1 0.5db 1 0 0 1 0 1.0db 1 0 0 1 1 1.5db 1 0 1 0 0 2.0db 1 0 1 0 1 2.5db 1 0 1 1 0 3.0db 1 0 1 1 1 3.5db 1 1 0 0 0 4.0db 1 1 0 0 1 4.5db 1 1 0 1 0 5.0db 1 1 0 1 1 5.5db 1 1 1 0 0 6.0db 1 1 1 0 1 6.5db 1 1 1 1 0 7.0db 1 1 1 1 1 7.5db table 11: txmod1 control register ($88)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 37 d/838/8 5.1.2.7 synthesizer baseband clk control register ($89) clock source bit 7 and bit 6 d7 d6 description 0 0 clock sources off (chip mostly powered down) 0 1 baseband clock source from xtal, synthesizer reference clock from ref in 1 0 baseband and synthesizer reference clock from ref in xtal amplifier disabled 1 1 baseband and synthesizer reference clock from ref in xtal amplifier enabled ref in frequency bit 5, 4, 3, and 2 d5 d4 d3 d2 ref in frequency (mhz) 0 0 0 0 4.0 0 0 0 1 8.0 0 0 1 0 9.6 0 0 1 1 12.0 0 1 0 0 12.8 0 1 0 1 14.4 0 1 1 0 16.8 0 1 1 1 24.0 1 0 0 0 10.25 1 0 0 1 10.475 1 0 1 0 20.95 1 0 1 1 21.25 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 n/a xtal/clock frequency bit 1 and 0 d1 d0 xtal/clock frequency (mhz) 0 0 4.0 0 1 8.0 1 0 9.6 1 1 12.0 table 12: synthesizer baseband clk control register ($89)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 38 d/838/8 5.1.2.8 synthesizer general control register ($8a) synthesizer power control bit 7 and bit 6 d7 d6 description 0 0 synthesizer is powered down 0 1 synthesizer is enabled. 1 0 synthesizer reference clock buffer is powered - the remainder of the synthesizer is powered down. 1 1 reserved for test mode. lock control bit 5 and bit 4 d5 d4 description 0 0 lock detect irq is masked 0 1 lock detect irq is enabled (status updated every phase comparison when the last two comparisons disagree) 1 0 lock detect irq is enabled (irq updated instantly for loss of lock, irq updated after 8 consecutive in-lock phase compares to indicate lock) 1 1 lock detect irq is enabled (irq updated after 4 out of lock comparisons during the last 8, irq updated after 16 consecutive in-lock phase compares to indicate lock). ihl bit 3 reference section 4.3.3 phase detector and charge pump d3 description 0 i chp = 40 i set 1 i chp = 80 i set polarity of charge pump output bit 2 d2 description 0 negative vco v/f slope 1 positive vco v/f slope) rf service bit 1 and bit 0 d1 d0 description 0 0 select frs channels (synth ref = 12.5khz ) 0 1 select pmr 446 channels (synth ref = 6.25khz) 1 0 select gmsr channels (synth ref = 12.5khz ) (this does not include the upper frequency band of gmrs which is reserved for duplex operation in a gmrs system) 1 1 generic system (rf and reference dividers are directly programmed) table 13: synthesizer general control register ($8a)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 39 d/838/8 5.1.2.9 synthesizer channel select register ($8b) bit 7 and bit 6 always set these two bits to logic 0. lock detect window bit 5 and bit 4 d5 d4 description 0 0 lock detect comparison window set to 20ns 0 1 lock detect comparison window set to 40ns 1 0 lock detect comparison window set to 60ns 1 1 lock detect comparison window set to 80ns channel select bit 3-0 rf carrier frequency (mhz) d3 d2 d1 d0 frs see note 1 pmr 446 see note 2 gmrs see note 3 0 0 0 0 n/a n/a n/a 0 0 0 1 462.5625 446.00625 462.5500 0 0 1 0 462.5875 446.01875 462.5625 0 0 1 1 462.6125 446.03125 462.5750 0 1 0 0 462.6375 446.04375 462.5875 0 1 0 1 462.6625 446.05625 462.6000 0 1 1 0 462.6875 446.06875 462.6125 0 1 1 1 462.7125 446.08125 462.6250 1 0 0 0 467.5625 446.09375 462.6375 1 0 0 1 467.5875 n/a 462.6500 1 0 1 0 467.6125 n/a 462.6625 1 0 1 1 467.6375 n/a 462.6750 1 1 0 0 467.6625 n/a 462.6875 1 1 0 1 467.6875 n/a 462.7000 1 1 1 0 467.7125 n/a 462.71250 1 1 1 1 n/a n/a 462.72500 note 1: $8a (d1 = 0, d0 = 0) note 2: $8a (d1 = 0, d0 = 1) note 3: $8a (d1 = 1, d0 = 0) reference divider for generic service mode bit 3-0 see note 2 d3 d2 d1 d0 reference divider output frequency (khz) 0 0 0 6.25 0 0 1 12.5 0 1 0 20.0 0 1 1 see note 1 25.0 note 1: see register $8d note 2: this section is used if register $8a (d1 = 1, d0 = 1) table 14: synthesizer channel select register ($8b) 5.1.2.10 synthesizer status register ($8c) this read register stores the lock detect status of the most recent 7 phase comparisons and the current state of the lock detect circuitry. refer to the synthesizer general control register ($8a) for information on lock detect control and irq behavior. d0 is the most recent comparison d6 is the least recent, and d7 is the current state.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 40 d/838/8 5.1.2.11 synthesizer 1st if offset register ($8d) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 if rf service synthesizer general control register ($8a) bits d1 and d0 are set to frs (=0), pmr 446 (=1) or gmrs (=2). these 16 bits represent a signed binary number for the offset from the tx frequency to mix down to the first if. the synthesizer will automatically offset the synthesized frequency when the general control register tx bit is clear. the offset will be equal to: synthesizer if offset (sifos) x reference oscillator frequency (synth ref ) note, synth ref is selected by the rf service control bits of the synthesizer general control register and sifos is a 16 bit signed number formed by bits d[15:0] d[15:0] = (if frequency offset)/ synth ref for example for a high side if of 21.4mhz d[15:0] = 1712 (06b0 hex) for frs and gmrs d[15:0] = 3424 (0d60 hex) for pmr 446 for a low side if of 45mhz d[15:0] = -3600 (f1f0 hex) for frs and gmrs d[15:0] = -7200 (e3e0 hex) for pmr 446 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 a4 a3 a2 a1 a0 if generic system rf service is selected, synthesizer general control register ($8a: d1= 1, d0 = 1); then the rf divider is directly programmed via synthesizer channel select register ($8b):d0=m11, sifos:d[15:5] = m[10:0], and sifos:d[4:0] = a[4:0] rf divider n = 32 x m[11:0] + a[4:0] in the generic service mode this register must be reloaded to switch between rx and tx to account for the first if offset. the synthesized frequency will be n x synth ref where synth ref is set via synthesizer channel select register ($8b):d[2:1] = r[1:0]. note the register synthesizer baseband clock control must also be set properly for the synth ref to come out right. 5.1.2.12 16 bit subaudio task data register ($8e) bit(s) description bit 15-0 this register is used to download 16 bit initialization/configuration data to the tone signaling processor. refer to section 4.2.4 for task descriptions. table 15: 16 bit subaudio task data register ($8e) 5.1.2.13 16 bit subaudio test data register ($8f) bit(s) description bit 15-0 this register is reserved for device test modes. table 16: 16 bit subaudio test data register ($8f) 5.1.2.14 synthesizer test register ($90) bit(s) description bit 7-0 this register is reserved for device test modes. table 17: synthesizer test register ($90)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 41 d/838/8 5.1.2.15 16 bit subaudio test read data register ($91) bit(s) description bit 15-0 this register is reserved for device test modes. table 18: 16 bit subaudio test read data register ($91) 5.1.2.16 tone signaling control register ($93) bit(s) description subaudio power control bit 7 and bit 6 these bits are dedicated to power control for the subaudio section. bit 7 bit 6 power level setting 0 0 power down (off) 0 1 enabled irq control bit 5 and bit 4 bit 5 bit 4 0 0 no irq 0 1 irq when detect status change 1 0 irq when detect status change and subaudio tone change detected 1 1 irq as in ?1 0? setting but detect algorithm modified to detect after a single qualifying measurement instead of the normal 2 agreeing measurements. this decreased response time comes at the expense of increased false response rate. subaudio task bit 3-0 bit 3 bit 2 bit 1 bit 0 cross reference section description normal run mode 0 0 0 0 4.2.4.1 normal operation 0 0 0 1 0 0 1 0 reserved for test 0 0 1 1 4.2.4.2 reserved for test (do not use these tasks) 0 1 0 0 4.2.4.3.1 enable/disable tone detector 0 1 0 1 4.2.4.3.2 program user defined subaudio tone 0 1 1 0 4.2.4.3.3 adjust detector band width rx configure 0 1 1 1 4.2.4.3.4 adjust no tone timer duration 1 0 0 0 4.2.4.4.1 select sub-audio tone from preprogrammed list 1 0 0 1 4.2.4.4.2 program user defined subaudio tone 1 0 1 0 4.2.4.4.3 program audio frequency ringing tone tx configure 1 0 1 1 4.2.4.4.4 program tx timer 1 1 0 0 4.2.4.5.1 enter fast initialization mode 1 1 0 1 4.2.4.5.2 quickly enable/disable multiple detectors 1 1 1 0 4.2.4.5.3 configure aux pin as output initialize and configure 1 1 1 1 4.2.4.5.4 soft reset table 19: tone signaling control register ($93)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 42 d/838/8 5.1.2.17 subaudio status register ($94) bit(s) description synth_irq bit 7 this bit indicates whether the synthesizer lock detector issued an irq since the last read of the synthesizer status register. once the lock detector issues an irq this bit becomes a logic ?1? and the chip irq pin is pulled low. synth_irq bit remains a logic ?1? until the synthesizer status register is read. however, the chip?s irq is cleared as soon as this subaudio status register is read. in other words, when servicing an irq, read the subaudio status register and check this bit to determine if the synthesizer needs servicing. decoder status bit 6 in rx mode, the decode status bit is a logic one when an enabled decoder senses that the input signal matches its center frequency and is of sufficient quality to decode in tx mode, bits 6-0 are normally zero, but take the decimal value 127 to indicate when the tx timer has expired. reading the status register resets bits 6-0 to zero as well as clearing the irq in tx mode to allow recurring indication of tx timer expiration. in rx mode, only the irq is cleared on reading this status register, while the decode status and tone index are maintained and continuously reported here. tone index number bit 5-0 refer to table 2 for supported tone list and their index numbers. index numbers 1-51 indicate a matching decoder (enabled decoder index may be reported before the full decode qualification of 2 matching measurements). in tx mode, bits 6-0 are normally zero, but take the decimal value 127 to indicate when the tx timer has expired. if the input signal does not contain a subaudio signal that matches an enabled decoder?s center frequency then the decoder status bit is a logic zero ? in this case the decoder index number is reported as: ? 62 if there is a significant subaudio frequency present outside the bandwidth of any enabled decoder. ? 63 if the no tone timer has expired indicating (i.e. there is no significant subaudio frequency present currently) ? 0 if no subaudio signal has been seen since the subaudio processor was enabled or most recently placed in rx mode. ? any enabled index, if the last frequency measurement indicates that enabled tone may be present but has not yet been fully qualified. table 20: subaudio status register ($94) 5.1.2.18 8 bit subaudio task data register ($95) bit(s) description bit 7-0 this register is used to download 8 bit initialization/configuration data to the subaudio processor. refer to section 4.2.4 for task descriptions. table 21: 8 bit subaudio task data register ($95)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 43 d/838/8 5.1.2.19 subaudio analog control register ($97) bit(s) description subaudio filter input select bit 15 bit 15 in conjunction with rx tx/ bit (bit 7) of the setup register ($80) controls the input signal source of the subaudio filter according to the following table: bit 15 rx tx/ input source 0 0 rxin pin 0 1 encoder d/a 1 0 encoder d/a 1 1 rxin pin bit 15 in conjunction with rx tx/ form the decode control signal of the subaudio analog block according to the above table. in normal operation, this bit should be a logic ?0?. subaudio low pass filter 1 gain bit 14 bit 14 in conjunction with rx tx/ bit (bit 7) of the setup register ($80) controls the gain of the subaudio low pass filter, which is the second subaudio filter stage. the low pass filter gain is set according to the following table: bit 14 rx tx/ gain (db) 0 0 +20 0 1 0 1 0 0 1 1 +20 the default gain setting is 0db for tx mode and +20db for rx mode. setting gain to +20db in tx mode will overdrive the low pass filter resulting in distorted signals. this bit should be a logic ?0? for normal operation. subaudio high pass filter/ low pass filter select bit 13 bit 13 in conjunction with rx tx/ bit (bit 7) of the setup register ($80) controls the subaudio filter characteristic of the 2 nd filter stage according to the following table: bit 13 rx tx/ characteristic 0 0 65hz high pass dc blocking filter 0 1 2khz low pass smoothing filter 1 0 2khz low pass smoothing filter 1 1 65hz high pass dc blocking filter the nominal gain of this 2 nd subaudio filter stage is 0db for hpf mode and ?18db for lpf mode. see bit 7 description for setting low pass filter 2 gain to 0db. this bit should be a logic ?0? for normal operation.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 44 d/838/8 bit(s) description tx subaudio level bit 12-8 bit 12 bit 11 bit 10 bit 9 bit 8 subaudio gain 0 0 0 0 0 off 0 0 0 0 1 -7.5db 0 0 0 1 0 -7.0db 0 0 0 1 1 -6.5db 0 0 1 0 0 -6.0db 0 0 1 0 1 -5.5db 0 0 1 1 0 -5.0db 0 0 1 1 1 -4.5db 0 1 0 0 0 -4.0db 0 1 0 0 1 -3.5db 0 1 0 1 0 -3.0db 0 1 0 1 1 -2.5db 0 1 1 0 0 -2.0db 0 1 1 0 1 -1.5db 0 1 1 1 0 -1.0db 0 1 1 1 1 -0.5db 1 0 0 0 0 0.0db 1 0 0 0 1 0.5db 1 0 0 1 0 1.0db 1 0 0 1 1 1.5db 1 0 1 0 0 2.0db 1 0 1 0 1 2.5db 1 0 1 1 0 3.0db 1 0 1 1 1 3.5db 1 1 0 0 0 4.0db 1 1 0 0 1 4.5db 1 1 0 1 0 5.0db 1 1 0 1 1 5.5db 1 1 1 0 0 6.0db 1 1 1 0 1 6.5db 1 1 1 1 0 7.0db 1 1 1 1 1 7.5db subaudio low pass filter 2 gain bit 7 setting to a logic ?1? forces 2 nd subaudio filter stage to have 0db gain in lpf mode, resulting in a gain boost of 18db over the normal setting. used in conjunction with bit 13 this can allow an rx signal path with pass band response down to dc with a nominal overall pass band gain of 22db. in normal operation, this bit should be a logic ?0?. subaudio filter output enable bit 6 this bit can be used to expose the subaudio filter output through the mod block in rx mode. normally the subaudio filter output is only connected to the mod block in tx mode. setting this bit to a logic ?1? connects the filter output to the mod block in both tx and rx modes. in normal operation, this bit should be a logic ?0?. dc restoration bit 5 set this bit to a logic ?1? to enable external dc restore mode. in external dc restore mode, an external capacitor to ground at the aux i/o pin is required to compensate for internal filter offsets. in normal operation, this bit should be a logic ?0?.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 45 d/838/8 bit(s) description rx subaudio level bit 4-0 these bits control the subaudio digitally controlled trimmer amplifier gain over the range +/-7.5db in 0.5db steps if the rx tx/ bit of the setup register (d7 of $80) is a logic ?0?. bit 4 bit 3 bit 2 bit 1 bit 0 subaudio gain 0 0 0 0 0 off 0 0 0 0 1 -7.5db 0 0 0 1 0 -7.0db 0 0 0 1 1 -6.5db 0 0 1 0 0 -6.0db 0 0 1 0 1 -5.5db 0 0 1 1 0 -5.0db 0 0 1 1 1 -4.5db 0 1 0 0 0 -4.0db 0 1 0 0 1 -3.5db 0 1 0 1 0 -3.0db 0 1 0 1 1 -2.5db 0 1 1 0 0 -2.0db 0 1 1 0 1 -1.5db 0 1 1 1 0 -1.0db 0 1 1 1 1 -0.5db 1 0 0 0 0 0.0db 1 0 0 0 1 0.5db 1 0 0 1 0 1.0db 1 0 0 1 1 1.5db 1 0 1 0 0 2.0db 1 0 1 0 1 2.5db 1 0 1 1 0 3.0db 1 0 1 1 1 3.5db 1 1 0 0 0 4.0db 1 1 0 0 1 4.5db 1 1 0 1 0 5.0db 1 1 0 1 1 5.5db 1 1 1 0 0 6.0db 1 1 1 0 1 6.5db 1 1 1 1 0 7.0db 1 1 1 1 1 7.5db table 22: subaudio analog control register ($97) 6 application notes 6.1 overview the purpose of this section is to describe the cmx838 from an application perspective to shorten the time to successfully develop cmx838-based designs. because the cmx838 integrates so many functions of an frs/pmr446/gmrs (hereinafter referred to collectively as frs) radio, an approach is taken to examine a radio design from a top level down with an emphasis on cmx838 functions. functions outside the cmx838, e.g. rf functions, are beyond the scope of this data bulletin and so are presented only in conceptual form for illustrative purposes.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 46 d/838/8 6.2 basic frs radio architecture an frs radio transmits a baseband voice signal using rf fm modulation in the uhf band. a form of selective calling is highly desirable in frs applications to help coordinate the use of the available rf channels. the most popular technique divides the available audio spectrum into two frequency bands, audio and subaudio, to allow simultaneous transmission of voice in the audio band and a control signal in the subaudio band. a transmitting radio combines audio voice and subaudio tone signals into a composite signal and fm modulates it into rf with properly adjusted frequency deviation and bandwidths. a receiving radio demodulates the rf signal to recover the baseband composite signal and decodes the embedded subaudio tone to control the loudspeaker signal path. this technique is used to enable loudspeaker operation only when the appropriate subaudio control signal is received with voice. an acronym for this technique is ctcss ? continuous tone controlled selective squelch. the advanced tone processing functions of the cmx838 support the use of subaudio tones to selectively call different groups of receivers. for example, a group call feature would allow selective calling of ?parents,? ?children? and ?entire family? groups to better coordinate radio use. frs radios usually support multiple rf channels via synthesized radio techniques to optimize cost and size. figure 23 and figure 24 are conceptual diagrams that identify the audio processing, subaudio (encoder and decoder), modulation, baseband clock, and synthesizer functions described above. note that because frs radios are half duplex, several of the functions shown serve both tx and rx modes of operation. audio processing level control rf synthesizer and charge pump xtal oscillator & base band clock generation subaudio tone encoder voice (audio) input signal + ref clock from tcxo + vco pa clocks rf input signal in out baseband crystal figure 23: basic frs radio tx architecture discriminator ceramic if lna audio processing rx input signal subaudio decoder loudspeaker control xtal oscillator & baseband clock generation ref clock from tcxo + vco clocks rf input signal speaker driver in out rf synthesizer and charge pump baseband crystal figure 24: basic frs radio rx architecture
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 47 d/838/8 6.3 cmx838 architectural overview the cmx838 integrates all the audio processing, tone signaling processor, modulation, baseband clock and synthesizer functions described in section 6.2, along with several other important functions to reduce cost, size and design time. its main function blocks are identified below. audio processing level control rf synthesizer and charge pump xtal oscillator & baseband clock generation tone signaling processor + clocks figure 25: cmx838 main function blocks the tone signaling processor includes many features that are not provided by typical subaudio tone processors. 6.4 detailed cmx838 architecture a detailed diagram of the cmx838 is shown below with its five main sections identified. the c-bus serial interface, not a main section, provides a convenient i/o port through which an external c can access and control the cmx838?s many functions using a minimum of signals and circuit board area. - + vbias lpf preemph hpf lpf lim lpf ctcss encode ctcss decoders + vbias vbias v dd v ss bias vbias 0/180 phase 0/180 phase 12 bit programmable reference counter + - programmable divider divide 32/33 phase detect charge pump lock detect baseband timing generation sv dd sv ss cbus serial interface voltage ref audio tone encode s rx notone / tx duration timer deemph voltage ref voltage ref bpf vbias 1 0 micout 3 micin 4 aux i/o 2 rxin 1 v dd 22 v ss 19 v bias 26 xtal 12 xtal 13 ref in 11 +rf in 9 -rf in 8 rxout 23 txmod1 21 txmod2 20 cmd data 17 rply data 16 irq 15 serial clock 18 cs 14 sv dd 7 sv ss 10 cp out 5 i set 6 a out 28 b out 27 a in 25 b in 24 audio processing level control synthesizer & charge pump tone signaling processor clock generation figure 26: cmx838 main sections
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 48 d/838/8 6.4.1 audio processing the audio processing section, shown in figure 27, supports both tx and rx operating modes with various switch paths and enable/disable functions. the features support both end user features (e.g. digital loudspeaker speaker volume control and digital mic gain control) and manufacturing operations (e.g. peak deviation trim testing). features include: ? high gain microphone input amplifier to directly support electret/condenser microphones ? auxiliary audio input to accept signals from a second audio source e.g. an external tone generator or via an internal path from the cmx838?s tone signaling processor ? microphone/auxiliary/discriminator source switch ? pre-emphasis filter with enable/disable ? digital microphone level control ? audio filters to band limit audio signals and convert externally applied square tones to call tones ? switch matrix to engage both ?forward? and ?reverse? external audio processing functions. ? deviation limiter with integrated voltage reference regulates output level for constant audio rf deviation without requiring an external voltage regulator. ? post deviation limiter filter ? tx output to modulator section path enable switch ? de-emphasis filter with enable/disable ? rx output digital volume control - + vbias lpf preemph hpf lpf lim voltage ref deemph micout 3 micin 4 aux i/o 2 rxin 1 rxout 23 a out 28 b out 27 a in 25 b in 24 processed tx audio to modulation section processed rx audio to loudspeaker path from the discriminator audio from an external electret mic or a higher level signal source alternate audio input e.g. call tone signals alternate external audio processing paths e.g. companding, scrambling, etc. a out to a in and b out to b in figure 27: audio processing
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 49 d/838/8 examples of ?rx from discriminator?, ?tx voice from microphone? and ?tx internally generated audio tone with loudspeaker enabled? paths are illustrated in figure 28, figure 29, and figure 30. - + vbias lpf preemph hpf lpf lim voltage ref deemph micout 3 micin 4 aux i/o 2 rxin 1 rxout 23 a out 28 b out 27 a in 25 b in 24 processed tx audio to modulation section rx volume control to loudspeaker path from the discriminator figure 28: example audio rx path - + vbias lpf preemph hpf lpf lim voltage ref deemph micout 3 micin 4 aux i/o 2 rxin 1 rxout 23 a out 28 b out 27 a in 25 b in 24 processed tx audio to modulation section rx volume control is muted or disabled from the discriminator audio from an external electret mic or a higher level signal source alternate audio input e.g. call tone signals alternate external audio processing paths e.g. companding, scrambling, etc. a out to a in and b out to b in figure 29: example audio tx voice path - + vbias lpf preemph hpf lpf lim voltage ref deemph micout 3 micin 4 aux i/o 2 rxin 1 rxout 23 a out 28 b out 27 a in 25 b in 24 processed tx tone audio to modulation section processed tx tone audio to loudspeaker path so user hears own transmitted audio call tone (rx volume control is not muted) from the discriminator alternate audio input e.g. call tone signals alternate external audio processing paths e.g. companding, scrambling, etc. a out to a in and b out to b in audio tone from tone signaling processor figure 30: example audio tx internally generated tone with loudspeaker enabled path
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 50 d/838/8 6.4.2 tone signaling processor the tone signaling processor, shown in figure 31, provides a unique combination of features that outperforms traditional approaches. it supports traditional subaudio ctcss tones with advanced, flexible, encode and decode functions to simplify radio designs and enable new frs radio features. the tone signaling processor can also generate audio tones suitable for call alert signals to eliminate the need for an external tone generator, if desired. internal signals are exposed via flexible switch paths to support user defined external circuits. features include: ? 51 parallel ctcss decoders can be individually enabled/disabled to perform ?flash? tone decoding on user activated tones in an internal tone ?watch list.? this architecture provides the performance to support rapid receive tone scanning, group calling and tone cloning? (automatic ctcss decoder configuration) end product functions without a decoder response time penalty. note that one tone must be applied to the decoders at any given time, consistent with normal ctcss practice. ? the ctcss encoder/decoder contains a pre-programmed set of 50 tone definitions. each tone is referenced by index for simple application program development. the 50 tone definitions include the entire tia-603 standard tone set with other common frequencies added. a 51 st user programmable tone allows a user to configure an arbitrary tone frequency. ? integrated voltage reference regulates ctcss encoder output level for constant subaudio rf deviation without requiring an external voltage regulator. ? digitally controlled subaudio output level to support various external radio modulation architectures. ? complete ctcss decoder status word provides a single decoder status bit to directly drive squelch control decisions in an external c. ? user configurable ctcss decoder notone timer (to adjust ctcss decoder dropout response), bandwidth (to adjust selectivity) and tx duration timer functions. ? high performance filters with selectable gain controls enhance end product radio sensitivity and support multiple design architectures e.g. both internal and external summing of subaudio and audio signals. ? audio tone generator for call alert signals. ? controllable switch paths and internal signal exposure to support user developed functions. lpf ctcss encode ctcss decoders audio tone encode voltage ref bpf vbias 1 0 aux i/o 2 rxin 1 subaudio output audio call tone output from the discriminator figure 31: tone signaling processor
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 51 d/838/8 examples of ?ctcss tone decoder?, ?ctcss tone encoder? and ?internal audio encoder? paths are illustrated in figure 32, figure 33, and figure 34. lpf ctcss encode ctcss decoders audio tone encode voltage ref bpf vbias 1 0 aux i/o 2 rxin 1 subaudio output audio call tone output from the discriminator tone (hz) 67.0 69.3 71.9 74.4 77.0 79.7 ... 225.7 233.6 241.8 250.3 decoder activated list yes no no yes no yes ... yes no yes yes figure 32: example ctcss tone decoder path lpf ctcss encode ctcss decoders audio tone encode voltage ref bpf vbias 1 0 aux i/o 2 rxin 1 subaudio output audio call tone output from the discriminator figure 33: example ctcss tone encoder path
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 52 d/838/8 lpf ctcss encode ctcss decoders audio tone encode voltage ref bpf vbias 1 0 aux i/o 2 rxin 1 subaudio output audio call tone output from the discriminator figure 34: example internal audio tone encoder path 6.4.3 level control the level control section, shown in figure 35, combines tx audio and subaudio signals using a summer, selectable switch paths, digitally controlled gains, and 0/180 phase selection to support a variety of radio tx architectures. synthesized radio transmitters can attenuate subaudio tone levels in a manner related to the subaudio tone frequency. this section, described below, supports several approaches to manage this aspect of designs based on synthesizers. ? use an fm modulator having flat subaudio response. this modulator can be driven by the composite sum of audio and subaudio signals to perform ?single point modulation.? ? apply audio signal to the synthesizer vco input and subaudio signal to the synthesizer reference oscillator voltage control input. this modulator requires separate audio and subaudio output signals with their relative levels trimmed to perform ?two point modulation.? some oscillators are reverse acting and so must have their driving signal inverted before it is applied. applications requiring summed audio and subaudio to be applied to both the modulator and synthesizer reference oscillator are also supported. ? use an fm modulator with attenuating subaudio response. this modulator must be driven by constant audio levels but subaudio frequency dependent subaudio levels. this driving signal is obtained by varying the subaudio tone level, according to subaudio tone frequency, and then summing it with the audio signal. + vbias vbias 0/180 phase 0/180 phase txmod1 21 txmod2 20 audio signal subaudio signal figure 35: level control
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 53 d/838/8 examples of ?single point modulation level?, ?two point modulation level? and ?single point modulation with varied subaudio level? paths are illustrated in figure 36, figure 37, and figure 38. + vbias vbias 0/180 phase 0/180 phase txmod1 21 txmod2 20 audio signal subaudio signal figure 36: example single point modulation level path + vbias vbias 0/180 phase 0/180 phase txmod1 21 txmod2 20 audio signal subaudio signal to vco input to vctcxo input figure 37: example two-point modulation level paths + vbias vbias 0/180 phase 0/180 phase txmod1 21 txmod2 20 audio signal to vco input subaudio signal with level, adjusted in tone signaling processor via uc control to compensate for fm modulator subaudio frequency response characteristics figure 38: example single point modulation with varied subaudio level paths
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 54 d/838/8 6.4.4 synthesizer and charge pump the synthesizer and charge pump section reduces component cost and size when compared with non- integrated alternatives. it also provides a simpler programming interface because it is focused on frs applications. when combined with an external vco and related circuits its features include: ? pre-programmed support for frs, pmr446 and gmrs rf standard frequencies via simple ?channel select? commands. ? lock detect function with irq indication, if enabled. ? direct control of synthesizer values for more flexible operation, if desired. ? support for several ref in reference clock frequencies. ? charge pump programmed via a combination of a two state internal selection and an external charge current setting resistor. ? charge pump polarity control via serial command. ? integrated voltage reference provides constant charge pump current without requiring an external voltage regulator. 12 bit programmable reference counter + - programmable divider divide 32/33 phase detect charge pump lock detect voltage ref ref in 11 +rf in 9 -rf in 8 cp out 5 i set 6 figure 39: synthesizer and charge pump 6.4.5 clock generation the clock generation section develops internal clocks to operate the audio processing, tone signaling processor and level control sections. the clock source can be externally supplied or internally developed from an external crystal (attached to pins 12 and 13) or from a ref in clock signal applied to the synthesizer & charge pump. when the latter is used, the external crystal can be omitted to save cost and space. several crystal and ref in clock frequencies are supported. clock generation also includes a timer that is used in both rx and tx modes. in rx mode it operates as a notone timer to qualify when a received subaudio tone has been removed. in tx mode it serves to time a transmission?s duration. baseband timing generation rx notone / tx duration timer xtal 12 xtal 13 ref in via synthesizer and charge pump section attach optional crystal internal clocks figure 40: clock generation
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 55 d/838/8 6.4.6 powersave functions independent powersave control is provided for groups of cmx838 functions to support power management schemes. the scope of each powersave control is somewhat independent of the five functional sections of the cmx838 to support practical operating scenarios as shown in figure 41 below. - + vbias lpf preemph hpf lpf lim lpf ctcss encode ctcss decoders + vbias vbias v dd v ss bias vbias 0/180 phase 0/180 phase 12 bit programmable reference counter + - programmable divider divide 32/33 phase detect charge pump lock detect baseband timing generation sv dd sv ss cbus serial interface voltage ref audio tone encode s rx notone / tx duration timer deemph voltage ref voltage ref bpf vbias 1 0 micout 3 micin 4 aux i/o 2 rxin 1 v dd 22 v ss 19 v bias 26 xtal 12 xtal 13 ref in 11 +rf in 9 -rf in 8 rxout 23 txmod1 21 txmod2 20 cmd data 17 rply data 16 irq 15 serial clock 18 cs 14 sv dd 7 sv ss 10 cp out 5 i set 6 a out 28 b out 27 a in 25 b in 24 ps2 ps4 ps5 ps6 ps3 ps1 ps1 = register $83, bits 7-6 ps2 = register $83, bits 5-4 ps3 = register $83, bits 3-2 ps4 = register $93, bits 7-6 ps5 = register $89, bit 6 ps6 = register $8a, bits 7-6 figure 41: powersave scope and related control registers 6.5 control registers illustrated this section illustrates the associations between some control register bit fields and corresponding cmx838 function blocks for quick reference. for detailed descriptions and definitions of c-bus transactions and registers, see section 5.1. 12 bit programmable reference counter + - programmable divider divide 32/33 phase detect baseband timing generation xtal 12 xtal 13 ref in 11 +rf in 9 -rf in 8 7 6 5 4 3 2 1 synthesizer & baseband clock control, address $89 0 figure 42: synthesizer to baseband clock control, $89
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 56 d/838/8 lpf preemph hpf lpf lim + vbias 0/180 phase voltage ref deemph rxout 23 txmod1 21 a out 28 b out 27 a in 25 b in 24 7 6 5 4 3 2 1 setup, address $80 0 lpf ctcss encode ctcss decoders v dd v ss audio tone encode voltage ref bpf vbias 1 0 aux i/o 2 rxin 1 v dd 22 v ss 19 - + vbias micout 3 micin 4 synthesizer offset figure 43: setup, $80 - + vbias lpf preemph hpf lpf lim lpf ctcss encode ctcss decoders v dd v ss voltage ref audio tone encode rx notone / tx duration timer deemph voltage ref bpf vbias 1 0 micout 3 micin 4 aux i/o 2 rxin 1 v dd 22 v ss 19 rxout 23 a out 28 b out 27 a in 25 b in 24 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 subaudio analog control, address $97 7 6 5 4 3 2 1 audio control, address $81 0 7 6 5 4 3 2 1 rx audio level control, address $82 0 figure 44: audio ($81), rx audio level ($82) and subaudio analog ($97) control
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 57 d/838/8 - + vbias lpf preemph hpf lpf lim lpf ctcss encode + vbias vbias 0/180 phase 0/180 phase voltage ref deemph voltage ref bpf micout 3 micin 4 aux i/o 2 rxin 1 rxout 23 txmod1 21 txmod2 20 a out 28 b out 27 a in 25 b in 24 7 6 5 4 3 2 1 audio power & bandwidth control, address $83 (power control) 0 7 6 5 4 3 2 1 audio power & bandwidth control, address $83 (power control) 0 7 6 5 4 3 2 1 audio power & bandwidth control, address $83 (power control) 0 7 6 5 4 3 2 1 audio power & bandwidth control, address $83 (bandwidth control) 0 figure 45: audio power and bandwidth control, $83 vbias vbias 0/180 phase 0/180 phase txmod1 21 txmod2 20 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 txmod 1 & 2 control, address $88 figure 46: txmod1 & txmod2 control, $88
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 58 d/838/8 6.6 application examples this section includes application examples in the form of ordered c-bus register lists. when listed, the register must be read or written to according to its defined type. 6.6.1 cmx838 initialization the cmx838?s many sections and functions must be initialized in proper sequence before they can be operated. this example describes an initialization routine that may be used to configure the device for: ? baseband clock generation from rf synthesizer clock ? device digitally controlled amplifiers (dca) set to normal power operation ? filters and deviation limiter set for normal power consumption ? synthesizer enabled and set to frs channels ? subaudio section memory cleared and ready for configuration data 6.6.1.1 register descriptions: general reset ($01) synthesizer baseband clock control ($89): 10010000b = $90 ? baseband and synthesizer reference clock from ref in, xtal amp disabled (10) ? ref in frequency 12.8mhz (0100) ? bits 1-0 are don?t cares as xtal is not used audio power and bandwidth control ($83): 01010100b = $54 ? modulation digitally controlled amplifiers (dca) and microphone amplifier configured for normal operation (01) ? audio filters, deviation limiter, and audio level dca configured for normal operation (01) ? de-emphasis network and rx audio out dca configured for normal operation (01) ? post deviation limiter lpf set to wide setting (0) ? bit 0 is unused (0) synthesizer general control ($8a): 01010100b = $54 ? synthesizer is enabled (01) ? lock detect irq is enabled, status updated every phase comparison when the last two comparisons disagree (01) ? magnitude of charge pump current is 40*iset (0) ? positive vco gain slope (1) ? frs channels selected (00) tone signaling control ($93): 01001111b = $4f ? enable power (01) ? no irq (00) ? subaudio processor ?soft reset? (1111) note: once the subaudio processor is in the ?soft reset? mode, any further tasks that are issued to the subaudio processor will cause it to enter the ?fast initialization? mode. in this mode, the tone detectors and encoders do not run. in order to resume normal operation from this ?fast initialization? mode, a task of $0 must be written to the tone signaling control register ($93). 6.6.2 tx, subaudio encoding, single point modulation this tx scenario configures the cmx838 as shown in figure 47, for: ? baseband clock generation from rf synthesizer clock ? input from microphone ? internal pre-emphasis ? hpf used ? limiter/lpf used ? de-emphasis bypassed (this configuration will not allow tx tone to be heard at speaker) ? ctcss encoder enabled ? audio + subaudio tones summed and presented at tx mod 1 (tx mod 2 set to vbias)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 59 d/838/8 6.6.2.1 register descriptions: general reset ($01): (if required) synthesizer baseband clock control ($89): 10010000b = $90 ? baseband and synthesizer reference clock from ref in, xtal amp disabled (10) ? ref in frequency 12.8mhz (0100) ? bits 1-0 are don?t cares as xtal is not used setup ($80): 11111110b = $fe ? tx enabled (1) ? audio input supplied by microphone output (11) ? audio signal passed through hpf to limiter (1111) ? bit 0 is unused (0) audio control ($81): 00010000b = $10 ? audio signal passed through pre-emphasis filter and hpf (000) ? audio level set to 0.0db (10000) rx audio level control ($82): 00010111b = $17 ? deviation limiter not bypassed (0) ? post deviation limiter lpf not bypassed (0) ? de-emphasis network not bypassed (0) ? rx volume control set to 0.0db (10111) audio power and bandwidth control ($83): 01010100b = $54 ? modulation digitally controlled amplifiers (dca) and microphone amplifier configured for normal operation (01) ? audio filters, deviation limiter, and audio level dca configured for normal operation (01) ? de-emphasis network and rx audio out dca configured for normal operation (01) ? post deviation limiter lpf set to wide setting (0) ? bit 0 is unused (0) tx mod 1 & 2 control ($88): 00000000 01110000b = $0070 ? tx mod 2 output set to vbias (000) ? tx mod 2 output gain set to off (00000) ? tx mod 1 output set to audio + tone (011) ? tx mod 1 output gain set to 0.0db (10000) synthesizer general control ($8a): 01010100b = $54 ? synthesizer is enabled (01) ? lock detect irq is enabled, status updated every phase comparison when the last two comparisons disagree (01) ? magnitude of charge pump current is 40*iset (0) ? positive vco gain slope (1) ? frs channels selected (00) synthesizer channel select ($8b): 00000001b = $01 ? bits 7 and 6 set to zero (00) ? lock detect comparison window set to +/- 20ns (00) ? frs channel 1 selected (0001) tone signaling control register ($93): 01001111b = $4f ? enable power (01) ? no irq (00) ? subaudio processor ?soft reset? (1111) 8 bit subaudio task data ($95) : 00010000b = $10 ? load 110.9hz tone (00010000)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 60 d/838/8 tone signaling control register ($93): 01001000b = $48 ? enable power for subaudio section (01) ? no irq (00) ? load ?select subaudio tone from preprogrammed list? task (1000) tone signaling control register ($93): 01000000b = $40 ? enable power for subaudio section (01) ? no irq (00) ? load ?normal operation? task (0000) subaudio analog control ($97): 00010000 00010000b = $1010 ? subaudio encoder output passed to subaudio filter input (0) ? subaudio lpf gain set to 0db (default for tx mode) (0) ? subaudio lpf configured as 2khz smoothing filter (0) ? tx subaudio level set to 0.0db (10000) ? tx subaudio filter gain counter set to 0 for normal operation (0) ? subaudio filter configuration set to 0 for normal operation (0) ? dc restoration set to 0 for normal operation (0) ? rx subaudio level set to 0.0db (10000) - + vbias lpf preemph hpf lpf lim lpf ctcss encode ctcss decoders + vbias vbias v dd v ss bias vbias 0/180 phase 0/180 phase 12 bit programmable reference counter + - programmable divider divide 32/33 phase detect charge pump lock detect baseband timing generation sv dd sv ss cbus serial interface voltage ref audio tone encode s rx notone / tx duration timer deemph voltage ref voltage ref bpf vbias 1 0 micout 3 micin 4 aux i/o 2 rxin 1 v dd 22 v ss 19 v bias 26 xtal 12 xtal 13 ref in 11 +rf in 9 -rf in 8 rxout 23 txmod1 21 txmod2 20 cmd data 17 rply data 16 irq 15 serial clock 18 cs 14 sv dd 7 sv ss 10 cp out 5 i set 6 a out 28 b out 27 a in 25 b in 24 figure 47: application example tx, subaudio encoding, single point modulation 6.6.3 rx, subaudio decode ctcss tone or tones this rx scenario configures the cmx838 for: ? baseband clock generation from rf synthesizer clock ? rx enabled ? input from rx in pin ? signal passed through lpf, hpf, and de-emphasis in audio path (limiter bypassed) ? ctcss decoder enabled with a tone ?watch list? configured, if desired 6.6.3.1 register descriptions: general reset ($01): (if required)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 61 d/838/8 synthesizer baseband clock control ($89): 10010000b = $90 ? baseband and synthesizer reference clock from ref in, xtal amp disabled (10) ? ref in frequency 12.8mhz (0100) ? bits 1-0 are don?t cares as xtal is not used setup ($80): 00111110b = $3e ? rx enabled (0) ? audio input signal supplied from rx input (01) ? audio signal passed through hpf out to limiter (1111) ? bit 0 is unused (0) audio control ($81): 01010000b = $50 ? first stage filtering configured as lpf (01) ? audio signal passed through hpf (0) ? audio level set to 0.0db (10000) rx audio level control ($82): 11010111b = $d7 ? deviation limiter bypassed (1) ? post deviation limiter lpf bypassed (1) ? audio signal passed through de-emphasis network (0) ? rx volume control set to 0.0db (10111) audio power and bandwidth control ($83): 01010100b = $54 ? modulation digitally controlled amplifiers (dca) and microphone amplifier configured for normal operation (01) ? audio filters, deviation limiter, and audio level dca configured for normal operation (01) ? de-emphasis network and rx audio out dca configured for normal operation (01) ? post-deviation limiter lpf set to wide setting (0) ? bit 0 is unused (0) tx mod 1 & 2 control ($88): 00000000 00000000b = $0000 ? tx mod 2 output set to vbias (000) ? tx mod 2 output gain set to off (00000) ? tx mod 1 output set to vbias (000) ? tx mod 1 output gain set to off (00000) synthesizer general control ($8a): 01010100b = $54 ? synthesizer is enabled (01) ? lock detect irq is enabled, status updated every phase comparison when the last two comparisons disagree (01) ? magnitude of charge pump current is 40*iset (0) ? positive vco gain slope (1) ? frs channels selected (00) synthesizer channel select ($8b): 00000001b = $01 ? bits 7 and 6 set to zero (00) ? lock detect comparison window set to +/- 20ns (00) ? frs channel 1 selected (0001) tone signaling control ($93): 01001111b = $4f ? enable power (01) ? no irq (00) ? subaudio processor ?soft reset? (1111) - this task is only required when the subaudio processor is enabled the first time after power up (?general reset? alone does not require the ?soft reset? task to be issued)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 62 d/838/8 8 bit subaudio task data ($95) : 10110010b = $b2 ? load hex value resulting from $80 logically ordered with $32 (?254.1hz tone select?) {10000000b | 00110010b} = 10110010b = $b2 ? when in rx mode and msb of $95 is ?1?, the desired tone(s) is (are) loaded onto the ?tone watch list? ? when in rx mode and msb of $95 is ?0?, the desired tone(s) is (are) removed from the ?tone watch list? tone signaling control ($93): 01010100b = $54 ? enable power for subaudio section (01) ? irq when detect status change (01) ? load ?enable/disable tone detector? task (0100) if desired, repeat tone loading and tone detector enabling steps (immediately prior two steps) to build a ?tone watch list.? tone signaling control ($93): 01010000b = $50 ? enable power for subaudio section (01) ? irq when detect status change (01) ? load ?normal operation? task (0000) subaudio analog control ($97): 00010000 00010000b = $1010 ? rx input passed to subaudio filter input (0) ? subaudio lpf gain set to +20db (default for rx mode) (0) ? subaudio lpf configured as 65hz high pass dc blocking filter (0) ? tx subaudio level set to 0.0db (10000) ? tx subaudio filter gain counter set to 0 for normal operation (0) ? subaudio filter configuration set to 0 for normal operation (0) ? dc restoration set to 0 for normal operation (0) ? rx subaudio level set to 0.0db (10000) 6.6.4 rx, multiple subaudio tone detect - tone cloning? this rx scenario configures the cmx838 for: ? baseband clock generation from rf synthesizer clock ? rx enabled ? input from rx in pin ? signal passed through lpf, hpf, and de-emphasis in audio path (limiter bypassed) ? ctcss decoder enabled, all tia-603 standard tones selected for detection (recognition) tone cloning? is a function that allows one frs radio to quickly identify and clone the ctcss tone setting transmitted by another radio. for end users, tone cloning? simplifies the setup and operation of frs radios the ctcss tone programming process on the radio?s user interface. after the cmx838?s tia-603 standard tone set tone decoders are activated in a tone ?watch list?, the cmx838 then will promiscuously listen for any of those tones and identify it when it is received. the identity can then be used to efficiently set up the cmx838 ctcss encoder to continue to use that tone. 6.6.4.1 register descriptions: general reset ($01): (if required) synthesizer baseband clock control ($89): 10010000b = $90 ? baseband and synthesizer reference clock from ref in, xtal amp disabled (10) ? ref in frequency 12.8mhz (0100) ? bits 1-0 are don?t cares as xtal is not used setup ($80): 00111110b = $3e ? rx enabled (0) ? audio input signal supplied from rx input (01) ? audio signal passed through hpf out to limiter (1111) ? bit 0 is unused (0)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 63 d/838/8 audio control ($81): 01010000b = $50 ? first stage filtering configured as lpf (01) ? audio signal passed through hpf (0) ? audio level set to 0.0db (10000) rx audio level control ($82): 11010111b = $d7 ? deviation limiter bypassed (1) ? post deviation limiter lpf bypassed (1) ? audio signal passed through deemphasis network (0) ? rx volume control set to 0.0db (10111) audio power and bandwidth control ($83): 01010100b = $54 ? modulation digitally controlled amplifiers (dca) and microphone amplifier configured for normal operation (01) ? audio filters, deviation limiter, and audio level dca configured for normal operation (01) ? de-emphasis network and rx audio out dca configured for normal operation (01) ? post deviation limiter lpf set to wide setting (0) ? bit 0 is unused (0) tx mod 1 & 2 control ($88): 00000000 00000000b = $0000 ? tx mod 2 output set to vbias (000) ? tx mod 2 output gain set to off (00000) ? tx mod 1 output set to vbias (000) ? tx mod 1 output gain set to off (00000) synthesizer general control ($8a): 01010100b = $54 ? synthesizer is enabled (01) ? lock detect irq is enabled, status updated every phase comparison when the last two comparisons disagree (01) ? magnitude of charge pump current is 40*iset (0) ? positive vco gain slope (1) ? frs channels selected (00) synthesizer channel select ($8b): 00000001b = $01 ? bits 7 and 6 set to zero (00) ? lock detect comparison window set to +/- 20ns (00) ? frs channel 1 selected (0001) tone signaling control ($93): 01001111b = $4f ? enable power (01) ? no irq (00) ? subaudio processor ?soft reset? (1111) this task is only required when the subaudio processor is enabled the first time after power up (?general reset? alone does not require the ?soft reset? task to be issued) 8 bit subaudio task data ($95) : 10111111b = $bf ? load hex value resulting from $80 logically ordered with $3f (?all tia-603 tones select?) - {10000000b | 00111110b} = 10111111b = $bf ? when in rx mode and msb of $95 is ?1?, the desired tone(s) is (are) loaded onto the ?tone watch list? ? when in rx mode and msb of $95 is ?0?, the desired tone(s) is (are) removed from the ?tone watch list? tone signaling control ($93): 01010100b = $54 ? enable power for subaudio section (01) ? irq when detect status change (01) ? load ?enable/disable tone detector? task (0100)
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 64 d/838/8 tone signaling control ($93): 01010000b = $50 ? enable power for subaudio section (01) ? irq when detect status change (01) ? load ?enable/disable tone detector? task (0000) subaudio analog control ($97): 00010000 00010000b = $1010 ? rx input passed to subaudio filter input (0) ? subaudio lpf gain set to +20db (default for rx mode) (0) ? subaudio lpf configured as 65hz high pass dc blocking filter (0) ? tx subaudio level set to 0.0db (10000) ? tx subaudio filter gain counter set to 0 for normal operation (0) ? subaudio filter configuration set to 0 for normal operation (0) ? dc restoration set to 0 for normal operation (0) ? rx subaudio level set to 0.0db (10000) 7 performance specification 7.1 electrical performance 7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current v dd -30 +30 ma v ss -30 +30 ma any other pin -20 +20 ma e1 package total allowable power dissipation at t amb = 25c 400 mw derating above 25c 5.3 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c d1 package total allowable power dissipation at t amb = 25c 550 mw derating above 25c 9 mw/c above 25c storage temperature -55 +125 c operating temperature -40 +85 c 7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss ) 2.7 5.5 v operating temperature -40 +85 c
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 65 d/838/8 7.1.3 operating characteristics details in this section represent design target values and are not currently guaranteed. for the following conditions unless otherwise specified: audio level 0db ref. = 400mv rms at 1khz v dd = 3.0v to 5.5v, t amb = -40c to 85c composite signal = 400mv rms at 1khz + 100mv rms noise + 40mv rms subaudio signal noise bandwidth = 5khz band limited gaussian notes min. typ. max. units dc parameters i dd 1, 2 all powersaved 0.2 0.3 ma rx operating ctcss +audio + synthesizer 11 15.1 ma ctcss +audio 2 2.4 ma tx operating ctcss +audio + synthesizer 11.3 15.4 ma ctcss +audio 2.3 2.7 ma c-bus interface input logic "1" 70% v dd input logic "0" 30% v dd input leakage current logic "1" or "0" -1.0 1.0 a input capacitance 7.5 pf output logic "1" i oh = 120a 90% v dd output logic "0" i ol = 360a 10% v dd "off" state leakage current v out = v dd 3 10 a analog voltages dc voltage at analog pins 50% v dd dc voltage at iset pin 1.26 v variation of dc voltage at iset pin <10% ac parameters tone decoder sensitivity (pure tone) 4, 11 15 mv rms ctcss composite signal response time 160 ms de-response time 160 ms frequency range 65 255 hz ctcss encoder frequency range 65 255 hz tone frequency resolution 0.3 % tone amplitude 4, 11 30 mv rms tone amplitude tolerance 10 -1.0 0 1.0 db total harmonic distortion 5 2.0 %
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 66 d/838/8 notes min. typ. max. units audio filters 6 high pass cut-off frequency (-3db) 300 hz passband gain (at 1.0khz) 0 db passband ripple with respect to gain at 1.0khz -3 +0.5 db stopband attenuation (250hz) 33.0 db residual hum and noise -50.0 dbp alias frequency 50 khz input low-pass cut-off frequency (-3db) 4500 hz passband gain (at 1.0khz) 0 db passband ripple with respect to gain at 1.0khz -3 +0.5 db stopband attenuation (15khz) -20 db residual hum and noise -50.0 dbp alias frequency 50 khz deviation limiter peak to peak voltage limit 1.87 2.1 2.36 v p-p variation 10 <0.5 db post-deviation limiter low-pass cut-off frequency (-3db) narrowband 3000 hz wideband 3500 hz passband gain (at 1.0khz) 0 db passband ripple with respect to gain at 1.0khz -3 +0.5 db stopband attenuation narrowband (10khz) -40 db wideband (10khz) -35 db residual hum and noise -50.0 dbp alias frequency 50 khz pre-emphasis 7 passband (+6db per octave) 300 3000 hz gain at 1.0khz 0 db residual hum and noise -50.0 dbp alias frequency 50 khz de-emphasis 7 passband (-6db per octave) 300 3000 hz gain at 1.0khz 0 db residual hum and noise -50.0 dbp alias frequency 50 khz
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 67 d/838/8 notes min. typ. max. units external processing paths ain, bin - input impedance 100 k ? aout, bout ? output impedance 2.0 k ? rxin input impedance 100 k ? auxiliary input/output (aux i/o) input impedance ? aux output disabled 100 k ? output impedance ? aux output enabled 100 k ? transmitter modulator drives mod.1 attenuator attenuation at 0db -0.2 0 0.2 db cumulative attenuation error with respect to attenuation at 0db -1.0 1.0 db mod.2 attenuator attenuation at 0db -0.2 0 0.2 db cumulative attenuation error with respect to attenuation at 0db -0.6 0.6 db xtal/clock input pulse width ('high' or 'low') 9 40.0 ns input impedance (at 100hz) 10.0 m ? gain input = 1mv rms at 100hz 20.0 db transmit input amplifier (microphone amplifier) maximum capacitive load 100 pf unity gain bw (unloaded) 5 mhz maximum closed loop gain 40 db slew rate 1 v/ s gain control amplifiers: mod1, mod2, rxout enabled - output swing 8 2.7 v p-p disabled - output impedance 100 k ? maximum capacitive load 150 pf unity gain bw (unloaded) 2.6 mhz slew rate 2.1 v/ s rf synthesizer rf input sensitivity -20 dbm minimum internal phase comparison frequency 6.25 khz rf input frequency 100 500 mhz maximum reference input frequency 25 mhz sinusoidal input voltage (mv rms ) 100 500 mv rms input impedance (real) 100 k ?
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 68 d/838/8 operating characteristics notes: 1. at v dd = 3.0v and t amb = 25c only. currents change with v dd . 2. not including any current drawn from the device by external circuitry. 3. irq pin. 4. with input gain components set as recommended in figure 2 and internal gains set to 0db. 5. measured at mod 1 or mod 2 output. 6. see section 4.1. 7. maximum internal signal gains are about 11db for the pre-emphasis filter and 12db for de-emphasis, thus to avoid supply rails and clipping, signals should be scaled appropriately. the +/-7.5db audio level amplifier can be used to scale signals for best sound quality. filter supply rails are approximately v dd -0.3v. for example to minimize the de-emphasis filter distortion at v dd = 3.0v keep signals below about 20 _ 10 2 2 3 . 0 gain db dd v ? ? ? =240mv rms at its input 8. resistive load of 10k ? , at v dd = 3.0v and t amb = 25c. 9. timing for an external input to the xtal/clock pin. 10. variation over voltage, temperature, and frequency. 11. level is independent of supply voltage. 7.1.4 timing c-bus timings (see figure 48) notes min. typ. max. units t cse cs -enable to clock-high time 100 - - ns t csh last clock-high to cs -high time 100 - - ns t loz clock-low to reply output enable time 0.0 - - ns t hiz cs -high to reply output 3-state time - - 1.0 s t csoff cs -high time between transactions 1.0 - - s t nxt inter-byte time 200 - - ns t ck clock-cycle time 200 - - ns t ch serial clock-high time 100 - - ns t cl serial clock-low time 100 - - ns t cds command data set-up time 75.0 - - ns t cdh command data hold time 25.0 - - ns t rds reply data set-up time 50.0 - - ns t rdh reply data hold time 0.0 - - ns maximum 30pf load on each c-bus interface line. note: these timings are for the latest version of the c-bus as embodied in the cmx838.
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 69 d/838/8 cs hi-z = level not important or undefined serial clock t cse t ck t cl t cds t rds t cdh t rdh 70% v dd 30% v dd t ch t ck t csh t loz command data command data serial clock reply data reply data 76543 21 0 76543 21 0 76543 21 0 t nxt t csoff t hiz figure 48: c-bus timing
frs/pmr446/gmrs family radio processor cmx838 ? 2003 cml microsystems plc 70 d/838/8 7.2 packaging figure 49: 28-pin tssop (e1) mechanical outline: order as part no. cmx838e1 figure 50: 28-pin soic (d1) mechanical outline: order as part no. CMX838D1
frs/pmr446/gmrs family radio processor cmx838 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. www.cmlmicro.com for faqs see: www.cmlmicro.com/products/faqs/ for a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm for detailed application notes: www.cmlmicro.com/products/applications/ oval park, langford, maldon, essex, cm9 6wg - england. tel: +44 (0)1621 875500 fax: +44 (0)1621 875600 sales: sales@cmlmicro.com technical support: techsupport@cmlmicro.com 4800 bethania station road, winston-salem, nc 27105 - usa. tel: +1 336 744 5050, 800 638 5577 fax: +1 336 744 5054 sales: us.sales@cmlmicro.com technical support: us.techsupport@cmlmicro.com no 2 kallang pudding road, #09 to 05/06 mactech industrial building, singapore 349307 tel: +65 6745 0426 fax: +65 6745 2917 sales: sg.sales@cmlmicro.com technical support: sg.techsupport@cmlmicro.com no. 218, tian mu road west, tower 1, unit 1008, shanghai kerry everbright city, zhabei, shanghai 200070, china. tel: +86 21 6317 4107 +86 21 6317 8916 fax: +86 21 6317 0243 sales: cn.sales@cmlmicro.com.cn technical support: sg.techsupport@cmlmicro.com

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